S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 527
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S9S12GN16F0VLF
Manufacturer Part Number
S9S12GN16F0VLF
Description
16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GN16F0VLF
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
16 KB
Data Ram Size
1024 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
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15.3.2.2
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
ETRIGCH[3:0]
Module Base + 0x0001
ETRIGSEL
SRES[1:0]
SMP_DIS
Reset
Field
6–5
3–0
W
7
4
R
ETRIGSEL
ATD Control Register 1 (ATDCTL1)
0
7
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-0
inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
no effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in
A/D Resolution Select — These bits select the resolution of A/D conversion results. See
coding.
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
as source for the external trigger. The coding is summarized in
1
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
If only AN0 should be converted use MULT=0.
SRES1
0
6
SRES1
Figure 15-4. ATD Control Register 1 (ATDCTL1)
0
0
1
1
MC9S12G Family Reference Manual, Rev.1.23
Table 15-3. ATDCTL1 Field Descriptions
SRES0
Table 15-4. A/D Resolution Coding
1
5
SRES0
0
1
0
1
SMP_DIS
0
4
Table
Description
15-5.
ETRIGCH3
A/D Resolution
10-bit data
Reserved
Reserved
1
8-bit data
3
Table
Analog-to-Digital Converter (ADC10B16CV2)
ETRIGCH2
15-5.
1
2
ETRIGCH1
1
1
Table 15-4
ETRIGCH0
for
1
0
529
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