S9S12GN48F0VLF Freescale Semiconductor, S9S12GN48F0VLF Datasheet - Page 223
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S9S12GN48F0VLF
Manufacturer Part Number
S9S12GN48F0VLF
Description
16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GN48F0VLF
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12GN48F0VLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1
2.4.3.30
Freescale Semiconductor
Address 0x0254 (G1, G2)
Address 0x0254 (G3)
Read: Anytime
Write: Anytime
DDRM
PERM
PERM
Field
Field
Reset
Reset
3-0
3-1
0
W
W
R
R
Port M data direction—
This bit determines whether the associated pin is a general-purpose input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Port M pull device enable—Enable pull device on input pin or wired-or output pin
This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related
polarity select register bit. If a pin is used as output this bit has only effect if used in wired-or mode with a pullup
device.
1 Pull device enabled
0 Pull device disabled
Port M pull device enable—Enable pull device on input pin or wired-or output pin
This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related
polarity select register bit. If a pin is used as output this bit has only effect if used in wired-or mode with a pullup
device.
If CAN is active the selection of a pulldown device on the RXCAN input will have no effect.
1 Pull device enabled
0 Pull device disabled
Port M Pull Device Enable Register (PERM)
0
0
0
0
7
7
Figure 2-31. Port M Pull Device Enable Register (PERM)
0
0
0
0
6
6
Table 2-54. DDRM Register Field Descriptions
Table 2-55. PERM Register Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
0
0
0
0
5
5
0
0
0
0
4
4
Description
Description
PERM3
3
0
3
0
0
PERM2
0
0
0
2
2
Port Integration Module (S12GPIMV1)
PERM1
PERM1
Access: User read/write
Access: User read/write
0
0
1
1
PERM0
PERM0
0
0
0
0
225
1
1
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