S9S12GN48F0VLF Freescale Semiconductor, S9S12GN48F0VLF Datasheet - Page 447
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S9S12GN48F0VLF
Manufacturer Part Number
S9S12GN48F0VLF
Description
16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GN48F0VLF
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12GN48F0VLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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12.3.2
This section describes in address order all the ADC12B8C registers and their individual bits.
12.3.2.1
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
Freescale Semiconductor
Module Base + 0x0000
WRAP[3-0]
Reset
Field
3-0
W
R
Reserved
Register Descriptions
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in
ATD Control Register 0 (ATDCTL0)
0
7
WRAP3 WRAP2 WRAP1 WRAP0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
0
0
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 12-2. Multi-Channel Wrap Around Coding
Figure 12-3. ATD Control Register 0 (ATDCTL0)
MC9S12G Family Reference Manual, Rev.1.23
Table 12-1. ATDCTL0 Field Descriptions
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
5
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
4
Multiple Channel Conversions (MULT = 1)
Description
Wraparound to AN0 after Converting
WRAP3
Table
1
3
12-2.
Reserved
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN7
AN7
AN7
AN7
AN7
AN7
AN7
AN7
Analog-to-Digital Converter (ADC12B8CV2)
WRAP2
1
1
2
WRAP1
1
1
WRAP0
1
0
449
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