MAX1245ACAP Maxim Integrated, MAX1245ACAP Datasheet - Page 10

• Manufacturer Part Number: MAX1245ACAP
• Description: Analog to Digital Converters - ADC Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX1245ACAP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.375 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Factory Pack Quantity: 66
• Voltage Reference: 2.048 V

+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
Table 1. Control-Byte Format
Table 2. Channel Selection in Single-Ended Mode (SGL/D D I I F F = 1)
Table 3. Channel Selection in Differential Mode (SGL/D D I I F F = 0)
10
SEL2
SEL2
BIT 7
(MSB)
START
BIT
7(MSB)
6
5
4
3
2
1
0(LSB)
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
______________________________________________________________________________________
SEL1
SEL1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
NAME
BIT 6
SEL2
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
SEL0
SEL0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DESCRIPTION
BIT 5
SEL1
The first logic “1” bit after CS goes low defines the beginning of the control byte.
These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF/2 to +VREF/2.
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
Selects clock and power-down modes.
PD1
0
0
1
1
CH0
CH0
+
+
–
PD0
0
1
0
1
CH1
CH1
+
+
–
BIT 4
SEL0
Mode
Power-down (I
Unassigned
Internal clock mode
External clock mode
CH2
+
CH2
+
–
CH3
UNI/BIP
+
Q
BIT 3
= 1.2µA)
CH3
+
–
CH4
+
CH4
+
–
SGL/DIF
BIT 2
CH5
+
CH5
+
–
CH6
+
BIT 1
PD1
CH6
+
–
CH7
+
CH7
+
–
(LSB)
BIT 0
COM
PD0
–
–
–
–
–
–
–
–