MAX1245ACAP Maxim Integrated, MAX1245ACAP Datasheet - Page 8

• Manufacturer Part Number: MAX1245ACAP
• Description: Analog to Digital Converters - ADC Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX1245ACAP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.375 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Factory Pack Quantity: 66
• Voltage Reference: 2.048 V

The MAX1245 analog-to-digital converter (ADC) uses a
successive-approximation conversion technique and
input track/hold (T/H) circuitry to convert an analog sig-
nal to a 12-bit digital output. A flexible serial interface
provides easy interface to microprocessors (µPs). No
external hold capacitors are required. Figure 3 is a
block diagram of the MAX1245.
The sampling architecture of the ADC’s analog compara-
tor is illustrated in the equivalent input circuit (Figure 4). In
single-ended mode, IN+ is internally switched to
CH0–CH7, and IN- is switched to COM. In differential
mode, IN+ and IN- are selected from the following pairs:
CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure
the channels with Tables 2 and 3.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as the
positive input (IN+) charges capacitor C
sition interval spans three SCLK cycles and ends on the
falling SCLK edge after the last bit of the input control
word has been entered. At the end of the acquisition inter-
val, the T/H switch opens, retaining charge on C
sample of the signal at IN+.
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
Figure 3. Block Diagram
8
_______________Detailed Description
SHDN
SCLK
VREF
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
DIN
CS
_______________________________________________________________________________________
18
19
17
10
11
1
2
3
4
5
6
7
8
9
REGISTER
ANALOG
INPUT
SHIFT
INPUT
MUX
MAX1245
CONTROL
LOGIC
T/H
Pseudo-Differential Input
IN
12-BIT
CLOCK
CLOCK
ADC
SAR
REF
INT
OUT
REGISTER
OUTPUT
SHIFT
HOLD
. The acqui-
15
12, 20
14
13
HOLD
16
DOUT
SSTRB
V
DGND
AGND
DD
as a
The conversion interval begins with the input multiplexer
switching C
negative input, IN- (In single-ended mode, IN- is simply
COM). This unbalances node ZERO at the input of the
comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
to 0V within the limits of 12-bit resolution. This action is
equivalent to transferring a charge of 16pF x [(V
(V
DAC, which in turn forms a digital representation of the
analog input signal.
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of
conversion, the positive input connects back to IN+,
and C
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
t
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by:
Figure 4. Equivalent Input Circuit
ACQ
IN
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
-)] from C
COM
, is the maximum time the device takes to acquire
CH0
CH1
CH2
CH3
CH6
CH4
CH5
CH7
HOLD
VREF
charges to the input signal.
HOLD
INPUT
MUX
|
t
IN+ - IN-
ACQ
HOLD
12-BIT CAPACITIVE DAC
C
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
SWITCH
–
from the positive input, IN+, to the
= 9 x (R
C
16pF
HOLD
to the binary-weighted capacitive
TRACK
SWITCH
+
|
is sampled. At the end of the
T/H
S
R
12k
IN
+ R
HOLD
ZERO
IN
) x 16pF
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
COMPARATOR
Track/Hold
IN
+
) -