MAX1245ACAP Maxim Integrated, MAX1245ACAP Datasheet - Page 11

• Manufacturer Part Number: MAX1245ACAP
• Description: Analog to Digital Converters - ADC Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX1245ACAP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.375 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Factory Pack Quantity: 66
• Voltage Reference: 2.048 V

perform a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the 12-bit
conversion result). See Figure 17 for MAX1245 QSPI
connections.
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 1.5MHz.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero and three trailing zeros.
The total conversion time is a function of the serial
clock frequency and the amount of idle time between
8-bit transfers. Make sure that the total conversion time
does not exceed 120µs, to avoid excessive T/H droop.
Figure 6. 24-Clock External-Clock-Mode Conversion Timing (MICROWIRE and SPI Compatible, QSPI Compatible with f
1) Set up the control byte for external clock mode and
2) Use a general-purpose I/O line on the CPU to pull
3) Transmit TB1 and, simultaneously, receive a byte
4) Transmit a byte of all zeros ($00 HEX) and, simulta-
5) Transmit a byte of all zeros ($00 HEX) and, simulta-
6) Pull CS high.
SSTRB
DOUT
A/D STATE
SCLK
DIN
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
CS low.
and call it RB1. Ignore RB1.
neously, receive byte RB2.
neously, receive byte RB3.
CS
START
1
SEL2 SEL1 SEL0 UNI/
______________________________________________________________________________________
IDLE
RB1
4
BIP
Simple Software Interface
(SCLK = 1.5MHz)
SGL/
DIF
ACQUISITION
2.0µs
t
ACQ
PD1
PD0
+2.375V, Low-Power, 8-Channel,
8
MSB
B11
B10
B9
12
RB2
In unipolar input mode, the output is straight binary
(Figure 14). For bipolar inputs, the output is two’s-com-
plement (Figure 15). Data is clocked out at the falling
edge of SCLK in MSB-first format.
The MAX1245 may use either an external serial clock or
the internal clock to perform the successive-approxima-
tion conversion. In both clock modes, the external clock
shifts data in and out of the MAX1245. The T/H acquires
the input signal as the last three bits of the control byte
are clocked into DIN. Bits PD1 and PD0 of the control
byte program the clock mode. Figures 7–10 show the
timing characteristics common to both modes.
In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
version. SSTRB pulses high for one clock period after
the control byte’s last bit. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
B8
CONVERSION
B7
B6
B5
16
Serial 12-Bit ADC
B4
B3
B2
B1
20
RB3
LSB
B0
FILLED WITH
ZEROS
IDLE
Clock Modes
External Clock
Digital Output
CLK
24
≤ 1.5MHz)
11