MK20DN512VLL10 Freescale Semiconductor, MK20DN512VLL10 Datasheet - Page 28
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MK20DN512VLL10
Manufacturer Part Number
MK20DN512VLL10
Description
ARM Microcontrollers - MCU Kinetis 512K
Manufacturer
Freescale Semiconductor
Datasheet
1.MK20DN512VLL10.pdf
(73 pages)
Specifications of MK20DN512VLL10
Rohs
yes
Core
ARM Cortex M4
Processor Series
MK20DN512
Data Bus Width
32 bit
Maximum Clock Frequency
100 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
A/d Bit Size
16 bit
A/d Channels Available
2
Interface Type
CAN, I2C, I2S, SPI, UART, USB
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Timers
2
On-chip Dac
Yes
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.71 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MK20DN512VLL10
Manufacturer:
FREESCALE
Quantity:
450
Peripheral operating requirements and behaviors
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
28
Symbol
Symbol
I
t
DDOSC
pll_lock
mode).
(Δf
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
each PCB and results will vary.
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
V
DD
dco_t
) over voltage and temperature should be considered.
Lock detector detection time
Supply voltage
Supply current — low-power mode (HGO=0)
Description
Description
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
Table 16. Oscillator DC electrical specifications
Table 15. MCG specifications (continued)
K20 Sub-Family Data Sheet, Rev. 2, 12/2012.
Table continues on the next page...
1.71
Min.
Min.
—
—
—
—
—
—
—
Typ.
Typ.
500
200
300
950
1.2
1.5
—
—
150 × 10
+ 1075(1/
f
Max.
pll_ref
Max.
3.6
—
—
—
—
—
—
Freescale Semiconductor, Inc.
)
-6
Unit
Unit
mA
mA
μA
μA
μA
nA
V
s
Notes
Notes
9
1