MK20DN512VLL10 Freescale Semiconductor, MK20DN512VLL10 Datasheet - Page 63

• Manufacturer Part Number: MK20DN512VLL10
• Description: ARM Microcontrollers - MCU Kinetis 512K
• Manufacturer: Freescale Semiconductor

Specifications of MK20DN512VLL10

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: MK20DN512
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• A/d Channels Available: 2
• Interface Type: CAN, I2C, I2S, SPI, UART, USB
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V

6.8.10.3 VLPR, VLPW, and VLPS mode performance over the full
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Freescale Semiconductor, Inc.
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Num.
Table 49. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
operating voltage range
(full voltage range)
S15
S15
Figure 27. I2S/SAI timing — slave modes
S12
Characteristic
S19
K20 Sub-Family Data Sheet, Rev. 2, 12/2012.
S13
S17
S11
S18
S12
S16
1.71
62.5
45%
250
45%
—
0
—
0
45
0
S15
Peripheral operating requirements and behaviors
Min.
3.6
—
55%
—
55%
45
—
45
—
—
—
Max.
V
ns
MCLK period
ns
BCLK period
ns
ns
ns
ns
ns
ns
S14
Unit
S16
S16
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