MK20DN512VLL10 Freescale Semiconductor, MK20DN512VLL10 Datasheet - Page 54

• Manufacturer Part Number: MK20DN512VLL10
• Description: ARM Microcontrollers - MCU Kinetis 512K
• Manufacturer: Freescale Semiconductor

Specifications of MK20DN512VLL10

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: MK20DN512
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• A/d Channels Available: 2
• Interface Type: CAN, I2C, I2S, SPI, UART, USB
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V

Peripheral operating requirements and behaviors
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I
6.8.4 CAN switching specifications
See
6.8.5 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
54
Symbol
I
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
LIM
General switching
Short circuit current
Description
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 40. Master mode DSPI timing (limited voltage range)
Table 39. USB VREG electrical specifications
specifications.
Description
K20 Sub-Family Data Sheet, Rev. 2, 12/2012.
(continued)
Min.
—
(t
(t
(t
SCK
BUS
BUS
2 x t
Min.
2.7
14
—
—
/2) − 2
2
2
0
0
x 2) −
x 2) −
BUS
Typ.
290
1
(t
SCK
Max.
3.6
25
—
—
—
—
—
—
/2) + 2
8
Max.
—
Freescale Semiconductor, Inc.
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
Unit
mA
Notes
Load
Notes
1
2
.