MPC8536BVTATLA Freescale Semiconductor, MPC8536BVTATLA Datasheet - Page 106

• Manufacturer Part Number: MPC8536BVTATLA
• Description: Microprocessors - MPU 8536 NON E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

CCB frequency
DDR Data Rate
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2. The processor core frequency speed bins listed also reflect the maximum platform (CCB) and DDR data rate frequency
Electrical Characteristics
2.23.1
This table provides the clocking specifications for the processor cores and
memory bus.
The DDR memory controller can run in either synchronous or asynchronous mode. When running in synchronous mode, the
memory bus is clocked relative to the platform clock frequency. When running in asynchronous mode, the memory bus is
clocked with its own dedicated PLL. This table provides the clocking specifications for the memory bus.
DDR Memory bus clock speed
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. The Memory bus clock refers to the chip’s memory controllers’ MCK[0:5] and MCK[0:5] output clocks, running at half of the
3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. See
106
e500 core processor frequency
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. See
“DDR/DDRCLK PLL
supported by production test. Running CCB and/or DDR data rate higher than the limit shown above, although logically possible
via valid clock ratio setting in some condition, is not supported.
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. See
Section 2.23.4, “DDR/DDRCLK PLL Ratio,”
DDR data rate.
the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency,
asynchronous mode must be used.
Ratio.”
data rate.
Characteristic
The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR
Characteristic
Clock Ranges
Section 2.23.2, “CCB/SYSCLK PLL
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Ratio,” for ratio settings.
Section 2.23.2, “CCB/SYSCLK PLL
Table 73. Processor Core Clocking Specifications
Table 74. Memory Bus Clocking Specifications
Min
600
400
400
600 MHz
Maximum Processor Core Frequency
Min
200
for ratio settings.
Max
600
400
400
600, 800, 1000, 1250
Maximum Processor Core Frequency
Ratio,”
Min
600
400
400
800 MHz
Section 2.23.3, “e500 Core PLL
Ratio,”
Max
800
400
400
Max
250
Section 2.23.3, “e500 Core PLL
Table 74
Min
600
333
400
1000 MHz
provides the clocking specifications for the
1000
Max
400
400
Section 2.23.4, “DDR/DDRCLK PLL
Ratio,“and
Min
MHz
600
333
400
Unit
1250 MHz
Freescale Semiconductor
1250
Max
500
500
Ratio,” and
Section 2.23.4,
MHz
Unit
1, 2, 3, 4
Notes
Notes
1, 2