MPC8536BVTATLA Freescale Semiconductor, MPC8536BVTATLA Datasheet - Page 25

• Manufacturer Part Number: MPC8536BVTATLA
• Description: Microprocessors - MPU 8536 NON E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

2.1.3
This table provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
2.2
The chip requires its power rails to be applied in a specific sequence in order to ensure proper chip operation. These
requirements are as follows for power up:
All supplies must be at their stable values within 50 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of theirs.
In order to guarantee MCKE low during power-up, the above sequencing for GV
of the DDR signals being in an indeterminate state during power-up, then the sequencing for GV
From a system standpoint, if any of the I/O power supplies ramp prior to the VDD platform supply, the I/Os associated with
that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the chip.
During the Deep Sleep state, the VDD core supply is removed. But all other power supplies remain applied. Therefore, there is
no requirement to apply the VDD core supply before any other power rails when the silicon waking from Deep Sleep.
Freescale Semiconductor
Local bus interface utilities signals
PCI signals
DDR2 signal
DDR3 signal
TSEC signals
DUART, system control, JTAG
I
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI1_GNT1 signal at reset.
3. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at T
2
C
1.
2.
3.
V
SV
[Wait for POWER_EN to assert], then V
GV
DD_PLAT
Power Sequencing
DD
DD
Output Driver Characteristics
,S2V
, V
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
DD
DD_CORE
Driver Type
, TV
DD
, XV
(if POWER_EN is not used to control V
DD
and X2V
Table 4. Output Drive Capability
DD
DD_CORE
(if POWER_EN is used to control V
32 (half strength mode)
40 (half strength mode)
Output Impedance
Programmable
42 (default)
45(default)
45(default)
125
150
DD_CORE
(Ω)
25
35
25
16
20
42
42
DD
), AV
j
is required. If there is no concern about any
= 105°C and at GV
DD
, BV
LV
DD
DD_CORE
GV
GV
BV
BV
BV
BV
BV
OV
OV
OV
DD
DD
, LV
Electrical Characteristics
Voltage
Supply
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
is not required.
= 2.5/3.3 V
DD
DD
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
= 1.8 V
= 3.3 V
= 1.8 V
= 1.5 V
= 3.3 V
= 3.3 V
, OV
)
(min)
DD
,
Notes
—
—
—
1
2
3
2
25