MPC8536BVTATLA Freescale Semiconductor, MPC8536BVTATLA Datasheet - Page 93

• Manufacturer Part Number: MPC8536BVTATLA
• Description: Microprocessors - MPU 8536 NON E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

2.20.2.2
The DC level requirement for the chip’s SerDes reference clock inputs is different depending on the signaling mode used to
connect the clock driver chip and SerDes reference clock inputs as described below.
Freescale Semiconductor
•
•
SD n _REF_CLK
SD n _REF_CLK
Differential Mode
— The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or
— For external DC-coupled connection, as described in
— For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since
Single-ended Mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be
— The SDn_REF_CLK input average voltage must be between 200 and 400 mV.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled
Figure 59. Differential Reference Clock Input DC Requirements (External DC-Coupled)
between 200mV and 800mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
Characteristics,” the maximum average current requirements sets the requirement for average voltage (common
mode voltage) to be between 100 mV and 400 mV.
for DC-coupled connection scheme.
the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has
its common mode voltage set to SnGND. Each signal wire of the differential inputs is allowed to swing below and
above the command mode voltage (SnGND).
AC-coupled connection scheme.
between 400mV and 800mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or
tied to ground.
reference clock input requirement for single-ended signaling mode.
externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused
phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.
DC Level Requirement for SerDes Reference Clocks
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
200 mV < Input Amplitude or Differential Peak < 800 mV
Figure 60
Figure 59
Section 2.20.2.1, “SerDes Reference Clock Receiver
shows the SerDes reference clock input requirement for
shows the SerDes reference clock input requirement
Figure 61
100 mV < Vcm < 400 mV
Electrical Characteristics
shows the SerDes
Vmax < 800 mV
Vmin > 0 V
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