MPC8536BVTATLA Freescale Semiconductor, MPC8536BVTATLA Datasheet - Page 108

• Manufacturer Part Number: MPC8536BVTATLA
• Description: Microprocessors - MPU 8536 NON E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

Electrical Characteristics
Please note that the DDR PLL reference clock input, DDRCLK, is only required in asynchronous mode.
The DDRCLKDR configuration register in the Global Utilities block allows the DDR controller to be run in a divided down
mode where the DDR bus clock is half the speed of the default configuration. Changing of these defaults must be completed
prior to initialization of the DDR controller.
2.23.5
The integrated PCI controller in this chip supports PCI input clock frequency in the range of 33–66 MHz. The PCI input clock
can be applied from SYSCLK in synchronous mode or PCI1_CLK in asynchronous mode. For specifications on the PCI1_CLK,
refer to the PCI 2.2 Specification.
The use of PCI1_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this range then use of
PCI1_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK.
108
TSEC_1588_TRIG_OUT[0:1],
TSEC1_1588_CLK_OUT
PCI Clocks
Functional Signals
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Reset Configuration
cfg_ddr_pll[0:2]
Table 77. DDR Clock Ratio
Name
Value (Binary)
000
001
010
011
100
101
110
111
DDR:DDRCLK Ratio
Synchronous mode
Reserved
Freescale Semiconductor
10:1
12:1
3:1
4:1
6:1
8:1