XRT91L80ES Exar, XRT91L80ES Datasheet - Page 20

• Manufacturer Part Number: XRT91L80ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L80ES

• Product Category: Bus Transceivers
• Rohs: yes

XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
The serial remote loopback function is activated by setting RLOOPS "High". When serial remote loopback is
activated, the high-speed serial receive data from RXIP/N is presented at the high-speed transmit output
TXOP/N, and the high-speed recovered clock is selected and presented to the high-speed transmit clock input
of the Retimer. During serial remote loopback, the high-speed receive data (RXIP/N) is also converted to
parallel data and presented at the low-speed receive parallel interface RXDO[3:0]P/N. The recovered receive
clock is also divided by 4 and presented at the low-speed clock output RXPCLKOP/N to synchronize the
transfer of the 4-bit received parallel data. A simplified block diagram of serial remote loopback is shown in
Figure 16.
F
RLOOPP controls a more comprehensive version of remote loop-back that can also be used in conjunction
with the de-jitter PLL that is phase locked to the recovered receive clock. In this mode, the received signal is
processed by the CDR, and is sent through the serial to parallel converter. At this point, the 4-bit parallel data
and clock are looped back to the transmit FIFO. Concurrently, if receive clock jitter attenuation is also
employed, the received clock is divided down in frequency and presented to the input of the integrated phase/
frequency detector and is compared to the frequency of a VCXO that is connected to the VCXO_INP/N inputs.
With the LOOPTM_JA configured to use the recovered receive clock as the reference and VCXO_SEL
asserted, the VCXO is phase locked to the recovered receive clock. The de-jittered clock is then used to retime
the transmitter, resulting in the re-transmission of the de-jittered received data out of TXOP/N. A FIFO reset
using FIFO_RST should follow immediately after enabling/disabling parallel remote loopback. A simplified
block diagram of parallel remote loopback is shown in Figure 17.
F
4.0 DIAGNOSTIC FEATURES
4.1
4.2
IGURE
IGURE
16. S
17. P
Serial Remote Loopback
Parallel Remote Loopback
Rx Parallel Output
Rx Parallel Output
ERIAL
ARALLEL
R
EMOTE
R
EMOTE
L
Parallel Remote Loopback
Serial Remote Loopback
OOPBACK
L
FIFO
OOPBACK
FIFO
SIPO
SIPO
PISO
PISO
24
Re-Timer
Re-Timer
CDR
CDR
Output Drivers
Input Drivers
Output Drivers
Input Drivers
LVPECL
LVPECL
LVPECL
LVPECL
Tx Serial Output
Tx Serial Output
Rx Serial Input
Rx Serial Input
xr
xr
xr
xr
REV. 1.0.0