XRT91L80ES Exar, XRT91L80ES Datasheet - Page 9

• Manufacturer Part Number: XRT91L80ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L80ES

• Product Category: Bus Transceivers
• Rohs: yes

xr
xr
REV. 1.0.0
TRANSMITTER SECTION
xr
xr
VCXO_LOCKEN
ALTFREQSEL
VCXO_LOCK
TXPCLKOP
TXPCLKON
VCXO_SEL
LOOPBW
CPOUT
N
AME
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVTTL,
LVTTL,
LVTTL,
LVTTL,
L
LVDS
EVEL
-
T
YPE
O
O
O
I
I
I
I
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
P10
P11
P
M6
M7
P1
N8
P3
P8
IN
Reference Clock Frequency Select
This pin is used to select the frequency of the REFCLKP/N
clock input to the CMU.
"Low" = 77.76 MHz (83.31 MHz for FEC)
"High" = 155.52 MHz (166.63 MHz for FEC)
This pin is provided with an internal pull-up.
De-Jitter VCXO Select Option
This pin selects either the normal REFCLKP/N or the de-jitter
VCXO_INP/N pin as a reference clock to the CMU.
"Low" = Normal REFCLKP/N reference clock
"High" = De-Jitter VCXO_INP/N reference clock
This pin is provided with an internal pull-down.
De-Jitter PLL Lock Detect
If the de-jitter PLL lock detect is enabled with pin P3 and the de-
jitter VCXO mode is selected by pin M6, this pin will assert
"High" when the PLL is locked.
"Low" = VCXO Out of Lock
"High" = VCXO Locked
De-Jitter PLL Lock Detect Enable
This pin enables the VCXO_INP/N lock detect circuit and
VCXO_LOCK pin N8 to be active.
"Low" = VCXO Lock Detect Disabled
"High" = VCXO Lock Detect Enabled
This pin is provided with an internal pull-down.
Charge Pump Output (for external VCXO)
The nominal output of the charge pump current is 250 A
CMU Loop Bandwidth Select
This pin is used to select the bandwidth of the clock multiplier
unit of the transmit path to a narrow or wide band. Use Wide
Band for clean reference signals and Narrow Band for noisy ref-
erences.
"Low" = Wide Band (4x)
"High" = Narrow Band (1x)
This pin is provided with an internal pull-down.
Transmit Parallel Clock Output
This 622.08 MHz clock can be used for the downstream device
to generate the TXDI[3:0]P/N data and TXPCLKIP/N clock
input. This enables the downstream device and the STS-48/
STM-16 transceiver to be in synchronization.
N
OTE
7
: The XRT91L80 can output a 666.51 MHz transmit clock
output for Forward Error Correction (FEC).
D
ESCRIPTION
XRT91L80