XRT91L80ES Exar, XRT91L80ES Datasheet - Page 37

• Manufacturer Part Number: XRT91L80ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L80ES

• Product Category: Bus Transceivers
• Rohs: yes

XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
B
D4
D3
D2
D1
D0
IT
TXCLKO16DIS Auxiliary Clock Disable
VCXO_SEL
FIFO_RST
AUTORST
LOOPBW
FIFO_
N
AME
T
ABLE
CMU Loop Band Width Select
This bit is used to select the bandwidth of the clock multiplier unit
of the transmit path to a narrow or wide band. Use Wide Band for
clean reference signals and Narrow Band for noisy references.
"0" = Wide Band (4x)
"1" = Narrow Band (1x)
VCXO De-Jitter Select
This bit selects either the normal REFCLKP/N or the de-jitter
VCXO_INP/N as a reference clock.
"0" = Normal REFCLKP/N Mode
"1" = De-Jitter VCXO Mode
This bit is used to control the activity of the auxiliary clock.
"0" = TXCLKO16P/N Enabled
"1" = TXCLKO16P/N Disabled
Automatic FIFO Overflow Reset
If this bit is set to "1", the STS-48/STM-16 transceiver will automat-
ically flush the FIFO upon an overflow condition. Upon power-up,
the FIFO should be manually reset by setting FIFO_RST to "1" for
a minimum of 2 TXPCLKOP/N cycles.
"0" = Manual FIFO reset required for Overflow Conditions
"1" = Automatically resets FIFO upon Overflow Detection
Manual FIFO Reset
FIFORST should be set to "1" for a minimum of 2 TXPCLKOP/N
cycles after powering up and during manual FIFO reset. After the
FIFO_RST bit is returned "Low," it will take 8 to 10 TXPCLKOP/N
cycles for the FIFO to flush out. Upon an interrupt indication that
the FIFO has an overflow condition, this bit is used to reset or flush
out the FIFO.
"0" = Normal Operation
"1" = Manual FIFO Reset
N
OTE
: To automatically reset the FIFO, see the FIFO_AUTORST
14: M
bit.
C
ONFIGURATION
ICROPROCESSOR
0 C
F
UNCTION
ONTROL
R
34
EGISTER
R
EGISTER
0
X
03
H
(0
B
X
IT
03
D
H
)
ESCRIPTION
Register
Type
R/W
R/W
R/W
R/W
R/W
xr
xr
xr
xr
(HW reset)
REV. 1.0.0
Default
Value
0
0
0
0
0