DAC1008D650HN/C1 NXP Semiconductors, DAC1008D650HN/C1 Datasheet
DAC1008D650HN/C1
Manufacturer Part Number
DAC1008D650HN/C1
Description
Digital to Analog Converters - DAC DL 10BIT DAC 650MSPS 2X 4X OR 8X INT
Manufacturer
NXP Semiconductors
Datasheet
1.DAC1008D650HNC1.pdf
(98 pages)
Specifications of DAC1008D650HN/C1
Rohs
yes
Factory Pack Quantity
260
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1. General description
2. Features and benefits
The DAC1008D650 is a high-speed 10-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier WCDMA
transmitters.
Because of its digital on-chip modulation, the DAC1008D650 allows the complex pattern
provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to
IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit
Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.
The DAC1008D650 also includes a 2, 4 or 8 clock multiplier which provides the
appropriate internal clocks and an internal regulation to adjust the output full-scale
current.
The input data format is serial according to JESD204A specification. This new interface
has numerous advantages over the traditional parallel one: easy PCB layout, lower
radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum
number of lanes of the DAC1008D650 is 4 and its maximum serial data rate is
3.125 Gbps.
The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output
clock period between several DAC devices. MDS incorporates modes: Master/slave and
All slave mode.
DAC1008D650
Dual 10-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating
with JESD204A interface
Rev. 3 — 31 January 2012
Dual 10-bit resolution
650 Msps maximum update rate
Selectable 2, 4 or 8 interpolation
filters
Input data rate up to 312.5 Msps
Very low noise cap free integrated PLL
32-bit programmable NCO frequency
Four JESD204A serial input lanes
1.8 V and 3.3 V power supplies
LVDS compatible clock inputs
IMD3: 80 dBc; f
f
ACPR: 64 dBc; two carriers WCDMA;
f
Typical 1.20 W power dissipation at
4 interpolation, PLL off and 640 Msps
Power-down mode and Sleep modes
Differential scalable output current from
1.6 mA to 22 mA
On-chip 1.29 V reference
External analog offset control
(10-bit auxiliary DACs)
Internal digital offset control
Inverse (sin x) / x function
o
s
= 640 Msps; f
= 140 MHz
s
o
= 640 Msps;
= 133 MHz
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