DAC1008D650HN/C1 NXP Semiconductors, DAC1008D650HN/C1 Datasheet - Page 58

• Manufacturer Part Number: DAC1008D650HN/C1
• Description: Digital to Analog Converters - DAC DL 10BIT DAC 650MSPS 2X 4X OR 8X INT
• Manufacturer: NXP Semiconductors

Specifications of DAC1008D650HN/C1

• Rohs: yes
• Factory Pack Quantity: 260

NXP Semiconductors
Table 79.
Default settings are shown highlighted.
Table 80.
Default settings are shown highlighted.
Table 81.
Default settings are shown highlighted.
DAC1008D650
Product data sheet
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
Symbol
SR_SWA_LN3
SR_SWA_LN2
SR_SWA_LN1
SR_SWA_LN0
SR_CA_LN3
SR_CA_LN2
SR_CA_LN1
SR_CA_LN0
Symbol
SR_CNTRL_LN3
SR_CNTRL_LN2
SR_CNTRL_LN1
SR_CNTRL_LN0
SR_DEC_LN3
SR_DEC_LN2
SR_DEC_LN1
SR_DEC_LN0
Symbol
FORCE_LOCK_LN3
FORCE_LOCK_LN2
FORCE_LOCK_LN1
FORCE_LOCK_LN0
10.15.2.8 Page 4 bit definition detailed description
SR_DLP_0 register (address 00h) bit description
SR_DLP_1 register (address 01h) bit description
FORCE_LOCK register (address 02h) bit description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 78
All information provided in this document is subject to legal disclaimers.
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
Rev. 3 — 31 January 2012
for a register overview and their default values. In the following
Value
0
0
0
0
Value
0
0
0
0
Value
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
2, 4 or 8 interpolating DAC with JESD204A
Description
soft reset clock_alignment lane 3
soft reset clock_alignment lane 2
soft reset clock_alignment lane 1
soft reset clock_alignment lane 0
Description
soft reset decoder_10b8b lane 3
soft reset decoder_10b8b lane 2
soft reset decoder_10b8b lane 1
soft reset decoder_10b8b lane 0
Description
lane 3 lock mode
lane 2 lock mode
lane 1 lock mode
lane 0 lock mode
soft reset sync_word_alignment lane 3
soft reset sync_word_alignment lane 2
soft reset sync_word_alignment lane 1
soft reset sync_word_alignment lane 0
soft reset controller lane 3
soft reset controller lane 2
soft reset controller lane 1
soft reset controller lane 0
automatic lock sync_word_alignment lane 3
manual lock sync_word_alignment lane 3
automatic lock sync_word_alignment lane 2
manual lock sync_word_alignment lane 2
automatic lock sync_word_alignment lane 1
manual lock sync_word_alignment lane 1
automatic lock sync_word_alignment lane 0
manual lock sync_word_alignment lane 0
DAC1008D650
© NXP B.V. 2012. All rights reserved.
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