iCE40LP1K-CM121 Lattice, iCE40LP1K-CM121 Datasheet - Page 27

• Manufacturer Part Number: iCE40LP1K-CM121
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM121

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 95
• Maximum Operating Frequency: 533 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-121
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 490

iCE40 External Switching Characteristics – LP Devices (Continued)
Generic DDR
Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using Global Pin for Clock Input –
GDDRX1_RX.SCLK.Aligned
t
t
f
f
Generic DDRTX1 Outputs with Clock and Data Aligned at Pin Using Global Pin for Clock Input –
GDDRX1_TX.SCLK.Aligned
t
t
f
f
7:1 LVDS Inputs - GDDR71_RX.SCLK.7:1
t
t
f
f
f
7:1 LVDS Outputs - GDDR71_TX.SCLK.7:1
t
t
f
f
f
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14V. Other
2. General I/O timing numbers based on LVCMOS 2.5, 0pf load.
3. These numbers are for general purpose usage. Duty cycle tolerance is +/-10%.
4. Generic DDR timing numbers based on LVDS25 inputs and LVDS25E outputs (for input, output, and clock ports).
5. Duty cycle is +/- 5% for system usage.
6. Supported on devices with a PLL.
7. iCE40LP4K/iCE40LP8K status is Preliminary.
DVA
DVE
DATA
DDRX1
DIA
DIB
DATA
DDRX1
DVA
DVE
DATA
DDR71
CLKIN
DVB
DVA
DATA
DDR71
CLKOUT
operating conditions can be extracted from the iCECube2 software.
Parameter
4, 6
Input Data Valid After CLK
Input Data Hold After CLK
DDRX1 Input Data Speed
DDRX1 SCLK Frequency
Output Data Invalid After CLK Output
Output Data Invalid Before CLK Output
DDRX1 Output Data Speed
DDRX1 SCLK frequency
Input Data Valid After CLK
Input Data Hold After CLK
DDR71 Serial Input Data Speed
DDR71 CLK Frequency
7:1 Input Clock Frequency (SCLK)
Output Data Valid Before CLK Output
Output Data Valid After CLK Output
DDR71 Serial Output Data Speed
DDR71 CLK Frequency
7:1 Output Clock Frequency (SCLK)
3
3
Over Recommended Operating Conditions
Description
3
3
3-14
All iCE40LP devices, Bank 3
All iCE40LP devices, Bank 3
All iCE40LP devices, Bank 3
All iCE40LP devices, Bank 3
Device
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Min.
—
—
—
—
—
—
—
Max.
—
1, 2, 3, 7
Units
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
UI
UI
ns
ns
UI
UI
ns
ns