iCE40LP1K-CM121 Lattice, iCE40LP1K-CM121 Datasheet - Page 9

• Manufacturer Part Number: iCE40LP1K-CM121
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM121

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 95
• Maximum Operating Frequency: 533 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-121
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 490

RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration.
By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block
can also be utilized as a ROM.
Note the sysMEM Embedded Block RAM Memory address 0 cannot be initialized.
Memory Cascading
Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks.
RAM4k Block
Figure 2-4 shows the 256x16 memory configurations and their input/output names. In all the sysMEM RAM modes,
the input data and addresses for the ports are registered at the input of the memory array.
Figure 2-4. sysMEM Memory Primitives
Table 2-5. EBR Signal Descriptions
For further information on the sysMEM EBR block, please refer to TN1250,
vices.
WDATA[15:0]
MASK[15:0]
WADDR[7:0]
WE
WCLKE
WCLK
RDATA[15:0]
RADDR[7:0]
RE
RCLKE
RCLK
Signal Name
Direction
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
WDATA[15:0]
WADDR[7:0]
MASK[15:0]
Write Port
WCLKE
WCLK
WE
Write Data input.
Masks write operations for individual data bit-lines.
0 = write bit; 1 = don’t write bit
Write Address input. Selects one of 256 possible RAM locations.
Write Enable input.
Write Clock Enable input.
Write Clock input. Default rising-edge, but with falling-edge option.
Read Data output.
Read Address input. Selects one of 256 possible RAM locations.
Read Enable input.
Read Clock Enable input.
Read Clock input. Default rising-edge, but with falling-edge option.
RAM Block
(256x16)
RAM4K
2-6
Description
RDATA[15:0]
RADDR[7:0]
Read Port
iCE40 LP/HX Family Data Sheet
RCLKE
RCLK
RE
Memory Usage Guide for iCE40 De-
Architecture