S25FL128SDPMFIG11 Spansion, S25FL128SDPMFIG11 Datasheet - Page 127

• Manufacturer Part Number: S25FL128SDPMFIG11
• Description: Flash 128Mb 3V 66MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SDPMFIG11

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: Flash
• Memory Size: 128 Mbit
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 100 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

July 12, 2012 S25FL128S_256S_00_05
10.8.11
SCK
CS#
SO
SI
Password Program (PASSP E8h)
Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded, the device sets the Write Enable Latch (WEL) to enable the PASSP operation.
The password can only be programmed before the Password Mode is selected by programming the
Password Protection Mode bit to 0 in the ASP Register (ASP[2]). After the Password Protection Mode is
selected the PASSP command is ignored.
The PASSP command is entered by driving CS# to the logic low state, followed by the instruction and the
password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is
sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64
PASSP command is not executed. As soon as CS# is driven to the logic high state, the self-timed PASSP
operation is initiated. While the PASSP operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PASSP
cycle, and is a 0 when it is completed. The PASSP command can report a program error in the P_ERR bit of
the status register. When the PASSP operation is completed, the Write Enable Latch (WEL) is set to a 0. The
maximum clock frequency for the PASSP command is 133 MHz.
MSB
7
0
CS#
SCK
SO
SI
6
1
Figure 10.80 Password Program Command Sequence
5
2
High Impedance
Instruction
4
D a t a
3
Figure 10.79 Password Read Command Sequence
MSB
7
3
0
S25FL128S and S25FL256S
4
6
1
S h e e t
2
5
5
2
High Impedance
Instruction
1
4
3
6
3
4
0
7
2
5
MSB
7
1
6
8
0
7
6
MSB
9
7
8
Password Least Sig. Byte First
5
6
10
9
th
Password
5
10
) bit of data has been latched. If not, the
4
11
59
68
58
58
69
69
57
70
57
56
70
71
MSB
7
56
72
71
127