S25FL128SDPMFIG11 Spansion, S25FL128SDPMFIG11 Datasheet - Page 67

• Manufacturer Part Number: S25FL128SDPMFIG11
• Description: Flash 128Mb 3V 66MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SDPMFIG11

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: Flash
• Memory Size: 128 Mbit
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 100 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

9.3
July 12, 2012 S25FL128S_256S_00_05
9.3.1
9.3.2
Block Protection
Freeze bit
Write Protect Signal
The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register
TBPROT bit can be used to protect an address range of the main flash array from program and erase
operations. The size of the range is determined by the value of the BP bits and the upper or lower starting
point of the range is selected by the TBPROT bit of the configuration register.
When Block Protection is enabled (i.e., any BP2-0 are set to 1), Advanced Sector Protection (ASP) can still
be used to protect sectors not protected by the Block Protection scheme. In the case that both ASP and Block
Protection are used on the same sector the logical OR of ASP and Block Protection related to the sector is
used. Recommendation: ASP and Block Protection should not be used concurrently. Use one or the other,
but not both.
Bit0 of the Configuration Register is the FREEZE bit. The FREEZE bit locks the BP2-0 bits in Status Register
1 and the TBPROT bit in the Configuration Register to their value at the time the FREEZE bit is set to 1. Once
the FREEZE bit has been written to a logic 1 it cannot be cleared to a logic 0 until a power-on-reset is
executed. As long as the FREEZE bit is cleared to logic 0 the status register BP bits and the TBPROT bit of
the Configuration Register are writable. The FREEZE bit also protects the entire OTP memory space from
programming when set to 1. Any attempt to change the BP bits with the WRR command while FREEZE = 1 is
ignored and no error status is set.
The Write Protect (WP#) input in combination with the Status Register Write Disable (SRWD) bit provide
hardware input signal controlled protection. When WP# is Low and SRWD is set to 1 the Status and
Configuration register is protected from alteration. This prevents disabling or changing the protection defined
by the Block Protect bits.
BP2
BP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Status Register Content
Status Register Content
D a t a
Table 9.1 Upper Array Start of Protection (TBPROT = 0)
Table 9.2 Lower Array Start of Protection (TBPROT = 1)
BP1
BP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S25FL128S and S25FL256S
S h e e t
BP0
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Protected Fraction
Protected Fraction
of Memory Array
of Memory Array
Upper 32nd
Lower 32nd
Upper 64th
Upper 16th
Lower 64th
Lower 16th
Upper Half
All Sectors
Lower Half
All Sectors
Upper 8th
Upper 4th
Lower 8th
Lower 4th
None
None
FL128S
FL128S
128 Mb
128 Mb
16384
16384
Protected Memory (kbytes)
Protected Memory (kbytes)
1024
2048
4096
8192
1024
2048
4096
8192
256
512
256
512
0
0
FL256S
FL256S
256 Mb
256 Mb
16384
32768
16384
32768
1024
2048
4096
8192
1024
2048
4096
8192
512
512
0
0
67