S25FL128SDPMFIG11 Spansion, S25FL128SDPMFIG11 Datasheet - Page 38
S25FL128SDPMFIG11
Manufacturer Part Number
S25FL128SDPMFIG11
Description
Flash 128Mb 3V 66MHz Serial NOR Flash
Manufacturer
Spansion
Datasheet
1.S25FL128SAGNFI001.pdf
(153 pages)
Specifications of S25FL128SDPMFIG11
Rohs
yes
Data Bus Width
1 bit
Memory Type
Flash
Memory Size
128 Mbit
Architecture
Uniform
Timing Type
Asynchronous
Interface Type
SPI
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Maximum Operating Current
100 mA
Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
SO-16
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6.3
38
6.2.1
6.3.1
Reset
Capacitance Characteristics
Power-On (Cold) Reset
Note:
1. For more information on capacitance, please consult the IBIS models.
The device executes a Power-On Reset (POR) process until a time delay of t
moment that V
and
i.e. no commands may be sent to the device until the end of t
is low during POR and remains low through and beyond the end of t
RESET# returns high. RESET# must return high for greater than t
hardware reset.
RESET#
RESET#
RESET#
Table 6.3 on page
VCC
VCC
CS#
VCC
CS#
VIO
C
CS#
VIO
VIO
C
OUT
IN
CC
rises above the minimum V
Input Capacitance (applies to SCK, CS#, RESET#)
39. The device must not be selected (CS# to go high with V
Output Capacitance (applies to All I/O)
tPU
tPU
tPU
Figure 6.6 POR followed by Hardware Reset
S25FL128S and S25FL256S
Figure 6.5 Reset High at the End of POR
Figure 6.4 Reset Low at the End of POR
Parameter
CS# must be high at tPU end
Table 6.2 Capacitance
CC
D a t a
tPU
tPU
If RESET# is low at tPU end
threshold. See
CS# may stay high or go low at tPU end
S h e e t
If RESET# is high at tPU end
PU
Figure 5.3 on page
. RESET# is ignored during POR. If RESET#
RS
Test Conditions
PU
before returning low to initiate a
1 MHz
1 MHz
, CS# must remain high until t
S25FL128S_256S_00_05 July 12, 2012
PU
tRS
has elapsed after the
35,
IO
Min
) during power-up (t
tRH
Table 5.2 on page
Max
8
8
RH
Unit
pF
pF
after
PU
35,
),
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