TSS461F-TDRZ-9 Atmel, TSS461F-TDRZ-9 Datasheet - Page 13
TSS461F-TDRZ-9
Manufacturer Part Number
TSS461F-TDRZ-9
Description
Network Controller & Processor ICs Van Data Link Controller
Manufacturer
Atmel
Datasheet
1.TSS461F-TDRZ-9.pdf
(57 pages)
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7615A–AUTO–02/06
Figure 7 shows a normal VAN bus frame. It is initiated with a Start of Frame (SOF) sequence
shown in Figure 9. The SOF can only be transmitted by an autonomous module. During the pre-
amble, the TSS461F will synchronize its bit rate clock to the data received.
Figure 9. Framing Sequences
When the complete SOF sequence has been transmitted or received, the circuit will start the
transmission or reception of the identifier field.
All data on the VAN bus, including the identifier and Frame Check Sum (FCS), are transmitted
using enhanced Manchester code.
In enhanced Manchester code, three NRZ bits are transmitted first followed by one Manchester
bit, then three more NRZ bits followed by one Manchester bit and so on.
Since the high state is recessive and the low state is dominant, the bus arbitration can be done.
If a module wants access to the bus, it must first listen to the bus during one full End of Frame
(EOF) and one full Inter Frame Spacing (IFS) period, to determine whether the bus is free or not
(i.e.,no dominant states received).
Figure 10. Data Encoding
The IFS is defined to be a minimum of 64 prescaled clocks periods. The TSS461F, accepts an
IFS of zero prescaled clocks for the reception only of a SOF sequence.
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
0
END OF
DATA
16
0
32
ACK
48
PREAMBLE
NRZ 0
START OF FRAME
8
64
MANCHESTER 0
MANCHESTER 1
80
96
16
END OF FRAME
112 128 144
NRZ 1
START
SYNC
24
160 176 192
32
TSS461F
13
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