TSS461F-TDRZ-9 Atmel, TSS461F-TDRZ-9 Datasheet - Page 6

• Manufacturer Part Number: TSS461F-TDRZ-9
• Description: Network Controller & Processor ICs Van Data Link Controller
• Manufacturer: Atmel

Microprocessor
Interface
Interface Modes
Intel Mode
6
TSS461F
The processor controls the TSS461F by reading and writing the internal registers of the circuit.
These registers appear to the processor as regular memory locations.
The TSS461F must be plugged in an Intel or Motorola environment with an 8-bit address/data
bus multiplexed.
Table 1. Access Mode Logic
In Intel environment, access operations need CS active, a read one with RD active, a write one
with WR active. If TSS461F is the single peripheral in the processor space, CS can be wired to
VCC.
In Motorola environment, the RD pin is wired to VSS and the access operations are driven by
CS (E). Contrary to Intel mode, CS (E) must never be wired to Vcc even if the TSS461F is alone.
To switch on-the-fly from one mode to the other, CS must be inactive.
The Intel mode interface consists of 13 pins. 8 pins are the multiplexed address and data bus,
and the rest are the address strobe, the read and write commands, the chip select and the inter-
rupt request pins.
To access the memory locations in Intel mode, the processor must first assert a valid address on
the multiplexed address and data bus and drive the address strobe pin high. When the required
set up time has passed, the processor must drive the address strobe low, and keep the address
valid for the required hold time.
The processor must then either assert the data to be written on the address and data bus, if a
write is intended, or float the data bus for a read. The next step is to drive either the write or read
command pins low, according to the function required, and at the same time drive the chip select
pin high.
The TSS461F access cycle is then terminated by driving the chip select and command pins low.
Note:
that the chip select pin may be driven high for the entire access cycle, and may also remain high
during and after the termination of the cycle.
CS (E)
0
1
1
1
1
RD
0
0
1
1
WR (R/W)
0
1
0
1
Operation Mode
No operation
Write Operation in Motorola mode
Read operation in both modes
Write operation in Intel mode
No operation
7615A–AUTO–02/06