XRT83SL216ES Exar, XRT83SL216ES Datasheet - Page 7

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XRT83SL216ES

Manufacturer Part Number
XRT83SL216ES
Description
Peripheral Drivers & Components - PCIs 16 CH E1 LIU SH
Manufacturer
Exar
Datasheet

Specifications of XRT83SL216ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
RECEIVER SECTION
REV. 1.0.0
RLOS15
RLOS14
RLOS13
RLOS12
RLOS10
RLOS11
RCLK15
RCLK14
RCLK13
RCLK12
RCLK11
RCLK10
RLOS9
RLOS8
RLOS7
RLOS6
RLOS5
RLOS4
RLOS3
RLOS2
RLOS1
RLOS0
RCLK9
RCLK8
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
N
AME
M10
R10
U12
N10
B10
D11
F10
B12
T12
A10
A11
E10
A12
U11
P10
T11
P
U8
R7
M8
C8
N8
U6
D8
T6
B6
B7
F8
T8
P7
A6
A7
E8
IN
T
YPE
O
O
Receive Loss of Signal
When a receive loss of signal occurs, the RLOS pin will go "High" for a mini-
mum of one RCLK cycle. RLOS will remain "High" until the loss of signal con-
dition clears. See the Receive Loss of Signal section of this datasheet for
more details.
Receive Clock Output
RCLK is the recovered clock from the incoming data stream. If the incoming
signal is absent, RCLK maintains its timing by using an internal master clock
as its reference. RPOS/RNEG data can be updated on either edge of RCLK
selected by RCLKinv in the appropriate channel register.
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
5
D
ESCRIPTION
XRT83SL216

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