P5010NXE1QMB Freescale Semiconductor, P5010NXE1QMB Datasheet - Page 124

• Manufacturer Part Number: P5010NXE1QMB
• Description: Processors - Application Specialized P5010 Ext TmpEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXE1QMB

• Rohs: yes

Electrical Characteristics
2.20.6.2.1
This table specifies AC requirements for SD_REF_CLKn and SD_REF_CLKn, where n = [2:3]. Only SerDes banks 2–3 may
be used for various SerDes XAUI configurations based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported
on SerDes bank 1.
2.20.6.2.2
This table defines the XAUI transmitter AC timing specifications. RefClk jitter is not included.
For recommended operating conditions, see
124
For recommended operating conditions, see
Deterministic jitter
Total jitter
Unit Interval: 3.125 GBaud
SD_REF_CLK/SD_REF_CLK frequency range
SD_REF_CLK/SD_REF_CLK clock frequency tolerance
SD_REF_CLK/SD_REF_CLK reference clock duty
cycle (measured at 1.6 V)
SD_REF_CLK/SD_REF_CLK cycle to cycle jitter
(period jitter at refClk input)
SD_REF_CLK/SD_REF_CLK total reference clock jitter
(peak-to-peak phase jitter at refClk input)
SD_REF_CLK/SD_REF_CLK rising/falling edge rate
Differential input high voltage
Differential input low voltage
Rising edge rate (SD_REF_CLKn) to falling edge rate
(SD_REF_CLKn) matching
Note:
1. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn).
2. Measurement taken from differential waveform
3. Measurement taken from single-ended waveform
4. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV
The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See
window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross
point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate
of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See
Table 77. XAUI AC SD_REF_CLKn and SD_REF_CLKn Input Clock Requirements (SV
Parameter
AC Requirements for XAUI SD_REF_CLKn and SD_REF_CLKn
XAUI Transmitter AC Timing Specifications
Parameter
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Table 78. XAUI Transmitter AC Timing Specifications
Table
Table
Symbol
3.
3.
J
J
UI
D
Figure
T
Figure
42.
320 – 100 ppm
41.
t
CLKRR/
Min
t
Matching
—
—
CLK_DUTY
Rise-Fall
t
t
Symbol
CLK_REF
CLK_TOL
t
t
CLK_CJ
CLK_PJ
V
V
IH
IL
t
CLKFR
Typical
320
—
—
–100
Min
–50
200
—
40
—
—
—
1
320 + 100 ppm
156.25
125/
Typ
Max
0.17
0.35
—
—
—
—
—
—
—
50
–200
Max
100
100
Freescale Semiconductor
50
20
—
—
60
4
UI p-p
UI p-p
Unit
ps
DD
= 1.0 V)
MHz
V/ns
Unit
ppm
mV
mV
ps
ps
%
%
Note
—
—
—
Note
3,
—
—
—
—
—
1
2
2
4