P5010NXE1QMB Freescale Semiconductor, P5010NXE1QMB Datasheet - Page 87

• Manufacturer Part Number: P5010NXE1QMB
• Description: Processors - Application Specialized P5010 Ext TmpEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXE1QMB

• Rohs: yes

2.12.3.3
This table provides the Ethernet management interface 1 AC timing specifications.
2.12.3.4
Freescale Semiconductor
For recommended operating conditions, see
For recommended operating conditions, see
MDC frequency
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
Note:
MDC frequency
MDC clock pulse width high
1. The symbols used for timing specifications follow the pattern of t
2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of
3. This parameter is dependent on the frame manager clock frequency. The delay is equal to 16 frame manager clock periods
4. t
inputs and t
management data timing (MD) for the time t
data hold time. Also, t
reaching the valid state (V) relative to the t
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
the MgmtClk Clock EC_MDC).
±6 ns. For example, with a frame manager clock of 333 MHz, the min/max delay is 48 ns ± 6 ns. Similarly, if the frame
manager clock is 400 MHz, the min/max delay is 40 ns ± 6 ns.
plb_clk
Parameter/Condition
is the frame manager clock period.
Parameter
(first two letters of functional block)(reference)(state)(signal)(state)
Ethernet Management Interface 1 AC Timing Specifications
Ethernet Management Interface 2 AC Electrical Characteristics
Table 42. Ethernet Management Interface 1 AC Timing Specifications
Table 43. Ethernet Management Interface 2 AC Timing Specifications
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
MDDVKH
symbolizes management data timing (MD) with respect to the time data input signals (D)
Symbol
t
t
t
MDKHDX
MDDVKH
MDDXKH
Table
Table 3.
Symbol
t
f
MDCH
t
MDC
MDCH
f
MDC
3.
MDC
1
MDC
1
clock reference (K) going to the high (H) state or setup time. For rise and fall
(16 × t
from clock reference (K) high (H) until data outputs (D) are invalid (X) or
Min
160
plb_clk
—
8
0
Min
160
—
) – 6
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
Typ
—
—
—
—
—
Typ
—
—
(16 × t
Max
plb_clk
2.5
—
—
—
Max
MDKHDX
2.5
—
) + 6
Electrical Characteristics
symbolizes
MHz
Unit
ns
ns
ns
ns
MHz
Unit
ns
Note
3,
—
—
—
Note
2
—
for
4
2
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