P5010NXE1QMB Freescale Semiconductor, P5010NXE1QMB Datasheet - Page 74

• Manufacturer Part Number: P5010NXE1QMB
• Description: Processors - Application Specialized P5010 Ext TmpEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXE1QMB

• Rohs: yes

Electrical Characteristics
This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.
2.9.2.2
This table contains the output AC timing targets for the DDR3 SDRAM interface.
74
For recommended operating conditions, see
For recommended operating conditions, see
1200 MT/s data rate
1066 MT/s data rate
800 MT/s data rate
Note:
MCK[n] cycle time
1. t
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
is captured with MDQS[n]. This should be subtracted from the total timing budget.
determined by the following equation: t
absolute value of t
CISKEW
MCK[n]
MCK[n]
MDQS[n]
MDQ[x]
Table 26. DDR3 and DDR3L SDRAM Interface Input AC Timing Specifications (continued)
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
DDR3 and DDR3L SDRAM Interface Output AC Timing Specifications
Table 27. DDR3 and DDR3L SDRAM Interface Output AC Timing Specifications
Parameter
Parameter
CISKEW
Figure 10. DDR3 and DDR3L SDRAM Interface Input Timing Diagram
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
.
Table
Table
DISKEW
t
t
MCK
DISKEW
3.
3.
Symbol
= ±(T ÷ 4 – abs(t
Symbol
t
DISKEW
t
MCK
1
D0
CISKEW
–275
–300
–425
D1
Min
Min
1.5
t
)) where T is the clock period and abs(t
DISKEW
t
DISKEW
Max
Max
275
300
425
2.5
DISKEW
Freescale Semiconductor
.This can be
Unit
Unit
ps
ns
CISKEW
Note
Note
) is the
2
2