P5010NXE1QMB Freescale Semiconductor, P5010NXE1QMB Datasheet - Page 145

• Manufacturer Part Number: P5010NXE1QMB
• Description: Processors - Application Specialized P5010 Ext TmpEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXE1QMB

• Rohs: yes

This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500-kHz to 10-MHz range. Each circuit
should be placed as close as possible to the specific AV
It should be possible to route directly from the capacitors to the AV
the inductance of vias, as shown in the following figure.
Where:
The AV
the power supplied to the PLL is filtered using a circuit similar to the one shown in following
effectiveness, the filter circuit is placed as closely as possible to the AV
possible. The ground connection should be near the AV
by two 2.2-µF capacitors, and finally the 1-Ω resistor to the board supply plane. The capacitors are connected from AV
to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept
short, wide, and direct.
Note the following:
3.3.2
XV
options to allow flexibility to address system noise dependencies.
An example solution for XV
when using DDR3, or CV
Freescale Semiconductor
DD
•
•
•
•
may be supplied by a linear regulator or sourced by a filtered 1.5 V or 1.8 V voltage source. Systems may design in both
DD_SRDSn
R = 5 Ω ± 5%
C1 = 10μF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH
C2 = 1.0 μF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH
AV
Signals on the SerDes interface are fed from the XV
Voltage for AV
An 0805 sized capacitor is recommended for system initial bring-up.
DD_SRDSn
XV
A higher capacitance value for C2 may be used to improve the filter as long as the other C2
parameters do not change (0402 body, X5R, ESL ≤ 0.5 nH).
Voltage for AV
signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock,
V
DD
DD_PL
should be a filtered version of SV
SV
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
DD_SRDSn
Power Supply Filtering
DD
DD
DD
at 1.8 V), is illustrated in
filtering, where 1.5 V or 1.8 V is sourced from voltage source (for example, GV
DD
Figure 55. SerDes PLL Power Supply Filter Circuit
is defined at the PLL supply filter and not the pin of AV
R
is defined at the PLL supply filter and not the pin of AV
1.0 Ω
Figure 54. PLL Power Supply Filter Circuit
C1
2.2 µF
DD_SRDSn
DD
Figure
GND
DD
1
pin being supplied to minimize noise coupled from nearby circuits.
NOTE
.
GND
DD
Low ESL Surface Mount Capacitors
56. The component values in this example filter is system
C2
power plane.
balls. The 0.003-µF capacitor is closest to the balls, followed
2.2 µF
DD
pin, which is on the periphery of the footprint, without
DD_SRDSn
1
AV
DD_PLAT
balls to ensure it filters out as much noise as
0.003 µF
, AV
DD_CCn
DD_SRDSn
Hardware Design Considerations
AV
DD
Figure
DD_SRDSn
.
, AV
DD_DDR
.
55. For maximum
DD
DD_SRDSn
at 1.5 V
145