CY7C1380D-167AXC Cypress Semiconductor Corp, CY7C1380D-167AXC Datasheet - Page 12
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CY7C1380D-167AXC
Manufacturer Part Number
CY7C1380D-167AXC
Description
IC SRAM 18MBIT 167MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Type
Synchronousr
Datasheet
1.CY7C1380D-167AXC.pdf
(34 pages)
Specifications of CY7C1380D-167AXC
Memory Size
18M (512K x 36)
Package / Case
100-LQFP
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Speed
167MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
3.4 ns
Maximum Clock Frequency
167 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3.135 V
Maximum Operating Current
275 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Ports
4
Operating Supply Voltage
3.3 V
Density
18Mb
Access Time (max)
3.4ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
167MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
19b
Package Type
TQFP
Operating Temp Range
0C to 70C
Supply Current
275mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
36b
Number Of Words
512K
Memory Configuration
1M X 18 / 512K X 36
Clock Frequency
167MHz
Supply Voltage Range
3.135V To 3.6V
Memory Case Style
TQFP
No. Of Pins
100
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-1629
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1380D-167AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C1380D-167AXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Company:
Part Number:
CY7C1380D-167AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380D/CY7C1382D incorporates a serial boundary
scan test access port (TAP).This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V
I/O logic levels.
The CY7C1380D/CY7C1382D contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
nally pulled up and may be unconnected. They may alternately
be connected to V
unconnected. Upon power up, the device comes up in a reset
state which does not interfere with the operation of the device.
TAP Controller State Diagram
The 0 or 1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Document #: 38-05543 Rev. *F
SS
1
0
) to prevent clocking of the device. TDI and TMS are inter-
TEST-LOGIC
RUN-TEST/
RESET
IDLE
0
1
DD
through a pull up resistor. TDO must be left
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
DR-SCAN
SHIFT-DR
EXIT1-DR
EXIT2-DR
1
SELECT
0
0
1
0
1
1
0
1
1
0
0
1
0
CAPTURE-IR
UPDATE-IR
PAUSE-IR
1
IR-SCAN
SHIFT-IR
EXIT1-IR
EXIT2-IR
SELECT
0
0
1
0
1
1
0
1
1
0
0
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an appli-
cation. TDI is connected to the most significant bit (MSB) of any
register. (See
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See
TAP Controller Block Diagram
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (V
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the
Upon power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
TMS
TCK
TDI
Selection
Circuitry
TAP Controller Block
TAP Controller State
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Boundary Scan Register
Identification Register
31
x
Instruction Register
TAP CONTROLLER
30
.
Bypass Register
29
.
.
.
TAP Controller Block
.
.
.
.
Diagram.)
Diagram.)
2
2
2
1
1
1
0
0
0
0
Circuitr
S
election
DD
y
) for five rising
Page 12 of 34
Diagram.
TDO
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