CY7C1380D-167AXC Cypress Semiconductor Corp, CY7C1380D-167AXC Datasheet - Page 9
![IC SRAM 18MBIT 167MHZ 100LQFP](/photos/6/76/67624/428-100-tqfp_14x20x1_4_sml.jpg)
CY7C1380D-167AXC
Manufacturer Part Number
CY7C1380D-167AXC
Description
IC SRAM 18MBIT 167MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Type
Synchronousr
Datasheet
1.CY7C1380D-167AXC.pdf
(34 pages)
Specifications of CY7C1380D-167AXC
Memory Size
18M (512K x 36)
Package / Case
100-LQFP
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Speed
167MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
3.4 ns
Maximum Clock Frequency
167 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3.135 V
Maximum Operating Current
275 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Ports
4
Operating Supply Voltage
3.3 V
Density
18Mb
Access Time (max)
3.4ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
167MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
19b
Package Type
TQFP
Operating Temp Range
0C to 70C
Supply Current
275mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
36b
Number Of Words
512K
Memory Configuration
1M X 18 / 512K X 36
Clock Frequency
167MHz
Supply Voltage Range
3.135V To 3.6V
Memory Case Style
TQFP
No. Of Pins
100
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-1629
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1380D-167AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C1380D-167AXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Company:
Part Number:
CY7C1380D-167AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Burst Sequences
The
provides a two-bit wraparound counter, fed by A1: A0, that imple-
ments an interleaved or a linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE
ADSP, and ADSC must remain inactive for the duration of t
after the ZZ input returns LOW.
Table 4. ZZ Mode Electrical Characteristics
Document #: 38-05543 Rev. *F
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Description
1
, CE
2
, CE
ZZREC
3
,
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Table 2. Interleaved Burst Address Table (MODE = Floating
or VDD)
Table 3. Linear Burst Address Table (MODE = GND)
Test Conditions
DD
DD
Address
Address
A1: A0
A1: A0
– 0.2V
– 0.2V
First
First
00
01
10
00
01
10
11
11
Address
Address
Second
Second
A1: A0
A1: A0
01
00
11
10
01
10
11
00
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
2t
Min
CYC
0
Address
Address
A1: A0
A1: A0
Third
Third
10
00
01
10
00
01
11
11
2t
2t
Max
80
CYC
CYC
Address
Address
Fourth
A1: A0
Fourth
A1: A0
Page 9 of 34
Unit
mA
ns
ns
ns
ns
11
10
01
00
11
00
01
10
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