HYB25D512800CE-6 Qimonda, HYB25D512800CE-6 Datasheet - Page 22

• Manufacturer Part Number: HYB25D512800CE-6
• Description: IC DDR SDRAM 512MBIT 66TSOP
• Manufacturer: Qimonda

Specifications of HYB25D512800CE-6

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1008-2

1)
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
Current State
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
Bank(s) Active
V
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
REF
must be maintained during Self Refresh operation
CKE n-1
Previous
Cycle
L
L
L
L
H
H
H
H
CKEn
Current
Cycle
L
H
L
H
L
L
L
H
Command n
X
Deselect or NOP
X
Deselect or NOP
Deselect or NOP
AUTO REFRESH
Deselect or NOP
See
Table 16
Date: 2007-12-13
22
Action n
Active Power-Down Entry
–
Maintain Self-Refresh
Exit Self-Refresh
Maintain Power-Down
Exit Power-Down
Precharge Power-Down Entry
Self Refresh Entry
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
Truth Table 3: Clock Enable (CKE)
512-Mbit Double-Data-Rate SDRAM
t
XSNR
) period. A minimum of 200
Internet Data Sheet
TABLE 15
Notes
1)
2)
–
–
–
–
–
–