ST62E32BF1 STMicroelectronics, ST62E32BF1 Datasheet - Page 31

• Manufacturer Part Number: ST62E32BF1
• Description: 8-bit Microcontrollers - MCU UV EPROM 8K SPI/UART
• Manufacturer: STMicroelectronics

Specifications of ST62E32BF1

• Product Category: 8-bit Microcontrollers - MCU
• Core: ST6
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 7948 B
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Package / Case: SDIP-42
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 21
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 30
• Number Of Timers: 1 x 8 bit
• Program Memory Type: EPROM
• Factory Pack Quantity: 13
• Supply Voltage - Max: 5 V
• Supply Voltage - Min: 4.5 V

INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused .
Bit 6 = LES: Level/Edge Selection bit .
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 11. Interrupt Requests and Mask Bits
GENERAL
TIMER
A/D CONVERTER
UART
ARTIMER
SPI
Port PAn
Port PBn
Port PCn
Port PDn
Port PEn
7
-
Peripheral
LES
ESB
IOR
TSCR1
ADCR
UARTCR
SCR1
SCR2
SCR3
SCR3
SCR3
SPI
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
ORPD-DRPD
ORPE-DRPE
GEN
Register
-
-
C8h
D4h
D1h
D7h
E8h
E1h
E2h
E2h
E2h
DCh
C0h-C4h
C1h-C5h
C2h-C6h
C3h-C7h
FCh-FDh
Address
Register
-
0
-
GEN
ETI
EAI
RXIEN
TXIEN
OVFIEN
CP1IEN
CP2IEN
ZEROIEN
CMPIEN
ALL
ORPAn-DRPAn
ORPBn-DRPBn
ORPCn-DRPCn PCn pin
ORPDn-DRPDn PDn pin
ORPEn-DRPEn
Mask bit
Bit 5 = ESB: Edge Selection bit .
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt . When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 IInterrupt sources
Interrupt
ST62E32B/T32B are summarized in the
with associated mask bit to enable/disable the in-
terrupt request.
All Interrupts, excluding NM
TMZ: TIMER Overflow
EOC: End of Conversion
RXRDY : Byte received
TXMT : Byte sent
OVFFLG: ARTIMER Overflow
CP1FLG
CP2FLG
ZEROFLG: Compare to zero flag
CMPFLG: Compare flag
End of Transmission
PAn pin
PBn pin
PEn pin
Masked Interrupt Source
sources
ST62T32B ST62E32B
available
I
on
All
source 4
source 4
source 4
source 3
source 1
source 1
source 2
source 0
source 2
source 1
Interrupt
Table 11
source
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the