ST62E32BF1 STMicroelectronics, ST62E32BF1 Datasheet - Page 63

• Manufacturer Part Number: ST62E32BF1
• Description: 8-bit Microcontrollers - MCU UV EPROM 8K SPI/UART
• Manufacturer: STMicroelectronics

Specifications of ST62E32BF1

• Product Category: 8-bit Microcontrollers - MCU
• Core: ST6
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 7948 B
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Package / Case: SDIP-42
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 21
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 30
• Number Of Timers: 1 x 8 bit
• Program Memory Type: EPROM
• Factory Pack Quantity: 13
• Supply Voltage - Max: 5 V
• Supply Voltage - Min: 4.5 V

4.6 SERIAL PERIPHERAL INTERFACE (SPI)
The on-chip SPI is an optimized serial synchro-
nous interface that supports a wide range of indus-
try standard SPI specifications. The on-chip SPI is
controlled by small and simple user software to
perform serial data exchange. The serial shift
clock can be implemented either by software (us-
ing the bit-set and bit-reset instructions), with the
on-chip Timer 1 by externally connecting the SPI
clock pin to the timer pin or by directly applying an
external clock to the Scl line.
The peripheral is composed by an 8-bit Data/shift
Register and a 4-bit binary counter while the Sin
pin is the serial shift input and Sout is the serial
shift output. These two lines can be tied together
to implement two wires protocols (I²C-bus, etc).
When data is serialized, the MSB is the first bit. Sin
has to be programmed as input. For serial output
Figure 39. SPI Block Diagram
Sout
SCL
Sin
I/O Port
I/O Port
I/O Port
1
0
OPR Reg.
Data Reg
Direction
Data Reg
Direction
Data Reg
Direction
DIN
CLK
DOUT
RESET
CP
CP
DIN
8-Bit Tristate Data I/O
operation Sout has to be programmed as open-
drain output.
The SCL, Sin and Sout SPI clock and data signals
are connected to 3 I/O lines on the same external
pins. With these 3 lines, the SPI can operate in the
following operating modes: Software SPI, S-BUS,
I²C-bus and as a standard serial I/O (clock, data,
enable). An interrupt request can be generated af-
ter eight clock pulses.
block diagram.
The SCL line clocks, on the falling edge, the shift
register and the counter. To allow SPI operation in
slave mode, the SCL pin must be programmed as
input and an external clock must be supplied to
this pin to drive the SPI peripheral.
In master mode, SCL is programmed as output, a
clock signal must be generated by software to set
and reset the port line.
(Q4=High after Clock8)
D0............................D7
to Processor Data Bus
SPI Interrupt Disable Register
Shift Register
4-Bit Counter
8-Bit Data
RESET
SPI Data Register
Enable
Output
DOUT
Reset
Load
Q4
Q4
Read
Write
Figure 39
ST62T32B ST62E32B
shows the SPI
Set Res
Interrupt
VR01504
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