ST62E32BF1 STMicroelectronics, ST62E32BF1 Datasheet - Page 61

• Manufacturer Part Number: ST62E32BF1
• Description: 8-bit Microcontrollers - MCU UV EPROM 8K SPI/UART
• Manufacturer: STMicroelectronics

Specifications of ST62E32BF1

• Product Category: 8-bit Microcontrollers - MCU
• Core: ST6
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 7948 B
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Package / Case: SDIP-42
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 21
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 30
• Number Of Timers: 1 x 8 bit
• Program Memory Type: EPROM
• Factory Pack Quantity: 13
• Supply Voltage - Max: 5 V
• Supply Voltage - Min: 4.5 V

4.5.4 DATA RECEPTION
The UART continuously looks for a falling edge on
the input pin whenever a transmission is not ac-
tive. Once an edge is detected it waits 1 bit time (8
states) to accommodate the Start bit, and then as-
sembles the following serial data stream into the
data register. The data in the ninth bit position is
copied into Bit 9, replacing any previous value set
for transmission. After all 9 bits have been re-
ceived, the Receiver waits for the duration of one
bit (for the Stop bit) and then transfers the received
data into the buffer register, allowing a following
character to be received. The interrupt flag
RXRDY is set to 1 as the data is transferred to the
buffer register and, if enabled, will generate an in-
terrupt.
If a transmission is started during the course of a
reception, the transmission takes priority and the
reception is stopped to free the resources for the
transmission. This implies that a handshaking sys-
tem must be implemented, as polling of the UART
to detect reception is not available.
Figure 38. UART Data Output
Table 20. Baud Rate Selection
UARTOE
TXD
PORT DATA
BR2
OUTPUT
0
0
0
0
1
1
1
1
BR2
0
0
1
1
0
0
1
1
1
0
MUX
BR0
0
1
0
1
0
1
0
1
VR02011
TXD1
f
INT
6.656
3.328
1.664
Division
832
416
256
208
4.5.5 INTERRUPT CAPABILITIES
Both reception and transmission processes can in-
duce interrupt to the core as defined in the inter-
rupt section. These interrupts are enabled by set-
ting TXIEN and RXIEN bit in the UARTCR register,
and TXMT and RXRDY flags are set accordingly
to the interrupt source.
4.5.6 REGISTERS
UART Data Register (UARTDR)
Address: D6h, Read/Write
Bit7-Bit0. UART data bits . A write to this register
loads the data into the transmit shift register and
triggers the start of transmission. In addition this
resets the transmit interrupt flag TXMT. A read of
this register returns the data from the Receive
buffer.
Warning . No Read/Write Instructions may be
used with this register as both transmit and receive
share the same address
D7
7
D6
f
INT
Reserved
D5
19200
31200
38400
1200
2400
4800
9600
= 8MHz
D4
Baud Rate
ST62T32B ST62E32B
D3
D2
f
INT
15600
19200
1200
2400
4800
9600
= 4MHz
600
D1
61/83
D0
0