ST62E32BF1 STMicroelectronics, ST62E32BF1 Datasheet - Page 50

• Manufacturer Part Number: ST62E32BF1
• Description: 8-bit Microcontrollers - MCU UV EPROM 8K SPI/UART
• Manufacturer: STMicroelectronics

Specifications of ST62E32BF1

• Product Category: 8-bit Microcontrollers - MCU
• Core: ST6
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 7948 B
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Package / Case: SDIP-42
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 21
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 30
• Number Of Timers: 1 x 8 bit
• Program Memory Type: EPROM
• Factory Pack Quantity: 13
• Supply Voltage - Max: 5 V
• Supply Voltage - Min: 4.5 V

ST62T32B ST62E32B
4.3.3 TIMINGS MEASUREMENT MODES
These modes are based on the capture of the
down counter content into either CP or RLCP reg-
isters. Some are used in conjunction with a syn-
chronisation of the down counter by reload func-
tions on external event on CPi pins or software
RUNRES setting, while other modes do not affect
the downcounting. As long as RELOAD bit is
cleared, the down counter remains in free running
mode.
4.3.3.1 Timing measurement with startup
control
Three startup conditions, selected by RLDSELi bit
can reload the counter from RLCP and initiate the
down counting when RELOAD bit is set. The first
mode is software controlled through the RUNRES
bit, while the two others are based on external event
on pins CP1 and CP2 with configurable polarities.
External event on CP2 pin (with configurable po-
larities) is used as strobe to launch the capture of
the CT counter into CP. When RELOAD bit is set,
RLCP cannot be used for capture, since it contains
the reload value..
Finally, 3 different Reload/Capture sequences are
available:
Figure 30. CP1 Triggered Restart Mode with CP2 Event Detection
50/83
RELOAD
COUNTER
RUNRES
1
0
CP2
CP1
CT
Disabled
Disabled
Reload on CP1,CP2, RUNRES / Capture CP2
Capture CP1 / Capture CP2
Enable the Inputs
0000h
Reload and Start
Set CP1FLG
Capture CT into CP
Set CP2FLG
Set CP1ERR
Reload
Set CP2ERR
Clear all Flags
– CP1 triggered restart mode with CP2 event de-
– CP2 triggered restart mode with second CP2
– Software triggered restart mode with CP2 event
CP1 triggered restart mode with CP2 event de-
tection.
This mode is enabled for RLDSEL2=0 and
RLDSEL1=1.
External events on CPi pins are enabled as soon as
RUNRES bit is set, which lets the prescaler and the
down counter running. The next active edge on CP1
causes the counter to be loaded from RLCP, the
CP1FLG to be set and the downcounting starts from
RLCP value. Each following active edge on CP1 will
cause a reload of the counter. If CP1FLG is not reset
before the next reload, the CP1ERR flag is set at the
same time as the counter is reloaded. Both flags
should then be cleared by software.
While the counter is counting, any active edge on
CP2 will capture the value of the counter at that in-
stant into the CP Register and set the CP2FLG bit.
If CP2FLG is not cleared before the following CP2
event, the CP2ERR flag bit is set, and no new cap-
ture can be performed
Capturing is re-enabled by clearing both CP2FLG
and CP2ERR.
If a capture on CP2 and a reload on CP1 occur at the
same time, the capture of the counter to CP is made
first, and then the counter is reloaded from RLCP.
tection.
event detection.
detection.
Set CP1FLG
Reload
Set CP1ERR, CP2FLG
First Capture in CP
Then Reload
Software Reset
Disabled
Disabled
VR02007
0000h