C8051F330DR Silicon Labs, C8051F330DR Datasheet - Page 107

• Manufacturer Part Number: C8051F330DR
• Description: 8-bit Microcontrollers - MCU 8kB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F330DR

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• On-chip Adc: No
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: QFN-20
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

12. External RAM
The C8051F330/1/2/3/4/5 devices include 512 bytes of RAM mapped into the external data memory
space. All of these address locations may be accessed using the external move instruction (MOVX) and
the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an
8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External
Memory Interface Control Register (EMI0CN as shown in SFR Definition 12.1). Note: the MOVX instruction
is also used for writes to the Flash memory. See
The MOVX instruction accesses XRAM by default.
For a 16-bit MOVX operation (@DPTR), the upper 7 bits of the 16-bit external data memory address word
are "don't cares". As a result, the 512-byte RAM is mapped modulo style over the entire 64 k external data
memory address range. For example, the XRAM byte at address 0x0000 is shadowed at addresses
0x0200, 0x0400, 0x0600, 0x0800, etc. This is a useful feature when performing a linear memory fill, as the
address pointer doesn't have to be reset when reaching the RAM block boundary.
Bits7–1: UNUSED. Read = 0000000b. Write = don’t care.
Bit 0:
R/W
Bit7
—
SFR Definition 12.1. EMI0CN: External Memory Interface Control
PGSEL: XRAM Page Select.
The EMI0CN register provides the high byte of the 16-bit external data memory address
when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. Since
the upper (unused) bits of the register are always zero, the PGSEL determines which page
of XRAM is accessed.
For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed.
R/W
Bit6
—
R/W
Bit5
—
R/W
Bit4
—
Rev. 1.7
Section “11. Flash Memory” on page 103
R/W
Bit3
—
R/W
Bit2
—
C8051F330/1/2/3/4/5
R/W
Bit1
—
SFR Address:
PGSEL
R/W
Bit0
0xAA
00000000
Reset Value
for details.
111