ST62T18CB6 STMicroelectronics, ST62T18CB6 Datasheet - Page 26

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ST62T18CB6

Manufacturer Part Number
ST62T18CB6
Description
8-bit Microcontrollers - MCU OTP EPROM 8K SPI/UAR
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST62T18CB6

Core
ST6
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Program Memory Size
7948 B
Data Ram Size
192 B
On-chip Adc
Yes
Operating Supply Voltage
3 V to 6 V
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
8 bit
A/d Channels Available
7
Data Rom Size
64 B
Interface Type
UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
12
Number Of Timers
1
Program Memory Type
EPROM
Factory Pack Quantity
20
Supply Voltage - Max
6 V
Supply Voltage - Min
3.6 V

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Part Number:
ST62T18CB6
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0
ST62T18C/E18C
DIGITAL WATCHDOG (Cont’d)
3.3.1 Digital Watchdog Register (DWDR)
Address: 0D8h — Read/Write
Reset status: 1111 1110 b
Bit 0 = C: Watchdog Control bit
If the hardware option is selected, this bit is forced
high and the user cannot change it (the Watchdog
is always active). When the software option is se-
lected, the Watchdog function is activated by set-
ting bit C to 1, and cannot then be disabled (save
by resetting the MCU).
When C is kept low the counter can be used as a
7-bit timer.
This bit is cleared to “0” on Reset.
Bit 1 = SR: Software Reset bit
This bit triggers a Reset when cleared.
When C = “0” (Watchdog disabled) it is the MSB of
the 7-bit timer.
This bit is set to “1” on Reset.
Bits 2-7 = T5-T0: Downcounter bits
It should be noted that the register bits are re-
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcounter and bit-2 (T5) is the MSB.
These bits are set to “1” on Reset.
26/82
26
T0
7
T1
T2
T3
T4
T5
SR
C
0
3.3.2 Application Notes
The Watchdog plays an important supporting role
in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
lated options should be selected on the basis of a
trade-off between application security and STOP
mode availability.
When STOP mode is not required, hardware acti-
vation without EXTERNAL STOP MODE CON-
TROL should be preferred, as it provides maxi-
mum security, especially during power-on.
When STOP mode is required, hardware activa-
tion and EXTERNAL STOP MODE CONTROL
should be chosen. NMI should be high by default,
to allow STOP mode to be entered when the MCU
is idle.
The NMI pin can be connected to an I/O line (see
Figure
ware. The I/O line can then be used to keep NMI
low while Watchdog protection is required, or to
avoid noise or key bounce. When no more
processing is required, the I/O line is released and
the device placed in STOP mode for lowest power
consumption.
When software activation is selected and the
Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
bits are in reverse order).
The software activation option should be chosen
only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions
should be executed within the first 27 instructions:
jrr 0, WD, #+3
ldi WD, 0FDH
18) to allow its state to be controlled by soft-

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