ST62T18CB6 STMicroelectronics, ST62T18CB6 Datasheet - Page 50

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ST62T18CB6

Manufacturer Part Number
ST62T18CB6
Description
8-bit Microcontrollers - MCU OTP EPROM 8K SPI/UAR
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST62T18CB6

Core
ST6
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Program Memory Size
7948 B
Data Ram Size
192 B
On-chip Adc
Yes
Operating Supply Voltage
3 V to 6 V
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
8 bit
A/d Channels Available
7
Data Rom Size
64 B
Interface Type
UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
12
Number Of Timers
1
Program Memory Type
EPROM
Factory Pack Quantity
20
Supply Voltage - Max
6 V
Supply Voltage - Min
3.6 V

Available stocks

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Part Number:
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ST62T18C/E18C
AUTO-RELOAD TIMER (Cont’d)
AR Status Control Register 1(ARSC1)
Address: E7h — Read/Write
Bist 7-5 = PS2-PS0: Prescaler Division Selection
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
following table:
Table 16. Prescaler Division Ratio Selection
Bit 4 = D4: Reserved . Must be kept reset.
Bit 3-2 = SL1-SL0: Timer Input Edge Control Bits 1-
0. These bits control the edge function of the Timer
input pin for external synchronization. If bit SL0 is re-
set, edge detection is disabled; if set edge detection
is enabled. If bit SL1 is reset, the AR Timer input pin
is rising edge sensitive; if set, it is falling edge sen-
sitive.
Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clock sources is explained in the following
3
Table 17. Clock Source Selection.
50/82
50
PS2
:
PS2
7
0
0
0
0
1
1
1
1
CC1
SL1
X
0
1
0
0
1
1
PS1
PS1
0
0
1
1
0
0
1
1
PS0
CC0
SL0
0
1
1
0
1
0
1
PS0
0
1
0
1
0
1
0
1
D4
F
F
ARTIMin Input Clock
Reserved
Disabled
Rising Edge
Falling Edge
int
int
Divided by 3
SL1
ARPSC Division Ratio
Edge Detection
Clock Source
SL0
128
16
32
64
1
2
4
8
CC1
Table
CC0
0
AR Load Register ARLR. The ARLR load register
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
AR Load Register (ARLR)
Address: EBh — Read/Write
Bit 7-0 = D7-D0: Load Register Data Bits. These
are the load register data bits.
AR Reload/Capture Register. The ARRC reload/
capture register is used to hold the auto-reload
value which is automatically loaded into the coun-
ter when overflow occurs.
AR Reload/Capture (ARRC)
Address: E9h — Read/Write
Bit 7-0 = D7-D0: Reload/Capture Data Bits . These
are the Reload/Capture register data bits.
AR Compare Register. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
Address: EAh — Read/Write
Bit 7-0 = D7-D0: Compare Data Bits . These are
the Compare register data bits.
D7
D7
D7
7
7
7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
0
0
0

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