ST62T18CB6 STMicroelectronics, ST62T18CB6 Datasheet - Page 55

• Manufacturer Part Number: ST62T18CB6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 8K SPI/UAR
• Manufacturer: STMicroelectronics

Specifications of ST62T18CB6

• Core: ST6
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 7948 B
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 6 V
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 7
• Data Rom Size: 64 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Program Memory Type: EPROM
• Factory Pack Quantity: 20
• Supply Voltage - Max: 6 V
• Supply Voltage - Min: 3.6 V

U. A. R. T (Cont’d)
4.5.4 Data Reception
The UART continuously looks for a falling edge on
the input pin whenever a transmission is not ac-
tive. Once an edge is detected it waits 1 bit time (8
states) to accommodate the Start bit, and then as-
sembles the following serial data stream into the
data register. First 8 bit are stored into the UART
Data Register, while the additionnal 9th bit is
stored into the LSB of the UART Control Register
in case of the 11-bit frame MCU option has been
selected. When the 10-bit frame option is selected,
the parity of the 8 received bit is automatically writ-
ten into the LSB of the UART Control Register
(PTYEN bit).
After all bit have been received, the Receiver waits
for the duration of one bit (for the Stop bit) and
then transfers the received data into the buffer reg-
ister, allowing a following character to be received.
The interrupt flag RXRDY is set to 1 as the data is
transferred to the buffer register and, if enabled,
will generate an interrupt.
Figure 33. Data Sampling Points
Table 19. Baudrate Selection
BR2
0
0
0
0
0
1
1
1
1
1
2
BR1
0
0
1
1
0
0
1
1
3
SAMPLES
1 BIT
4
5
BR0
0
1
0
1
0
1
0
1
6
7
VR02010
8
f
INT
6.656
3.328
1.664
Division
832
416
256
208
104
If a transmission is started during the course of a
reception, the transmission takes priority and the
reception is stopped to free the resources for the
transmission. This implies that a handshaking sys-
tem must be implemented, as polling of the UART
to detect reception is not available.
4.5.5 Interrupt Capabilities
Both reception and transmission processes can in-
duce interrupt to the core as defined in the inter-
rupt section. These interrupts are enabled by set-
ting TXIEN and RXIEN bit in the UARTCR register,
and TXMT and RXRDY flags are set accordingly
to the interrupt source.
4.5.6 Registers
UART Data Register (UARTDR)
Address: D6h, Read/Write
Bit7-Bit0. UART data bits . A write to this register
loads the data into the transmit shift register and
triggers the start of transmission. In addition this
resets the transmit interrupt flag TXMT. A read of
this register returns the data from the Receive
buffer. If the automatic even parity computation is
set (Bit PTYEN set), D7 must be cleared to 0 be-
fore transmission. Only the 7 LSB D0..D6 contain
the data to be sent.
Warning . No Read/Write Instructions may be
used with this register as both transmit and receive
share the same address
D7
7
D6
f
INT
D5
19200
31200
38400
76800
1200
2400
4800
9600
= 8MHz
D4
Baud Rate
D3
ST62T18C/E18C
D2
f
INT
15600
19200
38400
1200
2400
4800
9600
= 4MHz
600
D1
55/82
D0
0
55