ST62T18CB6 STMicroelectronics, ST62T18CB6 Datasheet - Page 30

• Manufacturer Part Number: ST62T18CB6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 8K SPI/UAR
• Manufacturer: STMicroelectronics

Specifications of ST62T18CB6

• Core: ST6
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 7948 B
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 6 V
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 7
• Data Rom Size: 64 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Program Memory Type: EPROM
• Factory Pack Quantity: 20
• Supply Voltage - Max: 6 V
• Supply Voltage - Min: 3.6 V

ST62T18C/E18C
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused .
Bit 6 = LES: Level/Edge Selection bit .
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 10. Interrupt Requests and Mask Bits
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GENERAL
TIMER
A/D CONVERTER
UART
ARTIMER
SPI
Port PAn
Port PBn
Port PDn
7
-
Peripheral
LES
ESB
IOR
TSCR1
ADCR
UARTCR
ARMC
SIDR
ORPA-DRPA
ORPB-DRPB
ORPD-DRPD
GEN
Register
-
-
C8h
D4h
D1h
D7h
E5h
DCh
C0h-C4h
C1h-C5h
C3h-C7h
Address
Register
-
GEN
ETI
EAI
RXIEN
TXIEN
OVIE
CPIE
EIE
ALL
ORPAn-DRPAn
ORPBn-DRPBn
ORPDn-DRPDn
0
-
Mask bit
Bit 5 = ESB: Edge Selection bit .
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt . When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt sources available on the ST62E18C/
T18C are summarized in the
ated mask bit to enable/disable the interrupt re-
quest.
All Interrupts, excluding NM
TMZ: TIMER Overflow
EOC: End of Conversion
RXRDY: Byte received
TXMT: Byte sent
OVF: ARTIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
End of Transmission
PAn pin
PBn pin
PDn pin
Masked Interrupt Source
Table 10
I
with associ-
All
source 4
source 4
source 4
source 3
source 1
source 1
source 2
source 2
Interrupt
source