NetduinoPlus2 Netduino, NetduinoPlus2 Datasheet
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ARM Cortex-M4 32b MCU+FPU, 210DMIPS 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Features ■ Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32F405xx, STM32F407xx 2.2.30 2.2.31 2.2.32 2.2.33 2.2.34 2.2.35 2.2.36 2.2.37 2.2.38 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20 5.3.21 5.3.22 5.3.23 5.3.24 5.3.25 5.3.26 5.3.27 5.3.28 6 Package characteristics . . . . . . . . . . . . . . . . . . . . ...
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STM32F405xx, STM32F407xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32F405xx, STM32F407xx Table 96. Main applications versus package for STM32F407xx microcontrollers . . . . . . . . . . . . . . 165 Table 97. Document revision history . . . . . . . . . ...
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List of figures List of figures Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64 . . . . . . . . . . . . 15 Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package ...
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STM32F405xx, STM32F407xx Figure 40. SPI timing diagram - master mode 2 Figure 41 slave timing diagram (Philips protocol) 2 Figure 42 master timing diagram (Philips protocol) Figure 43. USB OTG FS timings: definition of data signal ...
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List of figures Figure 88. USB controller configured as peripheral, host, or dual-mode and used in high speed mode ...
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STM32F405xx, STM32F407xx 1 Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the The STM32F405xx and STM32F407xx datasheet ...
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Description 2 Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM Cortex™-M4 32-bit RISC core operating at a frequency 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports ...
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Figure 5 shows the general block diagram of the device family. Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG Flash memory in Kbytes System SRAM in Kbytes Backup FSMC memory controller No Ethernet General-purpose Advanced-control Basic Timers ...
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Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued) Peripherals STM32F405RG Operating voltage Operating temperatures Package LQFP64 1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the ...
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STM32F405xx, STM32F407xx 2.1 Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pin- to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, ...
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Description Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package Ω Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package Ω 16/180 Doc ID 022152 Rev 3 STM32F405xx, STM32F407xx Ω Ω ...
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STM32F405xx, STM32F407xx Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 package Ω Doc ID 022152 Rev 3 Description 17/180 ...
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Description 2.2 Device overview Figure 5. STM32F40x block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to APB1 are clocked 18/180 Doc ID 022152 Rev 3 STM32F405xx, STM32F407xx ...
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... Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F405xx and STM32F407xx family is compatible with all ARM tools and software. Figure 5 shows the general block diagram of the STM32F40x family. ...
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Description 2.2.4 Embedded Flash memory The STM32F40x devices embed a Flash memory of 512 Kbytes or 1 Mbytes available for storing programs and data. 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used ...
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STM32F405xx, STM32F407xx Figure 6. Multi-AHB matrix 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB ...
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Description 2.2.9 Flexible static memory controller (FSMC) The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: ● Write ...
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STM32F405xx, STM32F407xx clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency ...
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Description All packages, except for the LQFP64 and LQFP100, have an internal reset controlled through the PDR_ON signal. 2.2.16 Voltage regulator The regulator has eight operating modes: ● Regulator ON/internal reset ON – Main regulator mode (MR) – Low power ...
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STM32F405xx, STM32F407xx Figure 7. Regulator ON/internal reset OFF Regulator OFF This mode allows to power the device as soon as V ● Regulator OFF/internal reset ON This mode is available only on UFBGA and WLCSP90 packages activated by ...
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Description allows to supply externally a 1.2 V voltage source through V addition to V The following conditions must be respected: – V should always be higher than V DD between power domains. – PA0 should be kept low to ...
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STM32F405xx, STM32F407xx 2.2.17 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F405xx and STM32F407xx includes: ● The real-time clock (RTC) ● 4 Kbytes of backup SRAM ● 20 backup registers The real-time clock (RTC) is ...
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Description and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI ...
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STM32F405xx, STM32F407xx Table 3. Timer feature comparison Counter Counter Timer type Timer resolution Advanced- TIM1, 16-bit control TIM8 Up/down TIM2, 32-bit TIM5 Up/down TIM3, 16-bit TIM4 Up/down TIM9 16-bit General purpose TIM10, 16-bit TIM11 TIM12 16-bit TIM13, 16-bit TIM14 TIM6, ...
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Description General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 3 for differences). ● TIM2, TIM3, TIM4, TIM5 The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 ...
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STM32F405xx, STM32F407xx SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: ● A 24-bit downcounter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0 ...
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Description Table 4. USART feature comparison USART Standard Modem LIN name features (RTS/CTS) USART1 X X USART2 X X USART3 X X UART4 X - UART5 X - USART6 X X 2.2.23 Serial peripheral interface (SPI) The STM32F40x feature up ...
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STM32F405xx, STM32F407xx 2.2.25 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I achieve error-free I performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I disabling the main PLL (PLL) used ...
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Description The STM32F407xx includes the following features: ● Supports 10 and 100 Mbit/s rates ● Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F46x reference manual for details) ● Tagged MAC frame support ...
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STM32F405xx, STM32F407xx The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that ...
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Description 2.2.34 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of ...
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... Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. Doc ID 022152 Rev 3 Description ...
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Pinouts and pin description 3 Pinouts and pin description Figure 10. STM32F40x LQFP64 pinout 38/180 ...
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STM32F405xx, STM32F407xx Figure 11. STM32F40x LQFP100 pinout Doc ID 022152 Rev 3 Pinouts and pin description 39/180 ...
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Pinouts and pin description Figure 12. STM32F40x LQFP144 pinout 40/180 Doc ID 022152 Rev 3 STM32F405xx, STM32F407xx ...
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STM32F405xx, STM32F407xx Figure 13. STM32F40x LQFP176 pinout Doc ID 022152 Rev 3 Pinouts and pin description 41/180 ...
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Pinouts and pin description Figure 14. STM32F40x UFBGA176 ballout 1. This figure shows the package top view. 42/180 Doc ID 022152 Rev 3 STM32F405xx, STM32F407xx ...
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STM32F405xx, STM32F407xx Figure 15. STM32F40x WLCSP90 ballout 1. This figure shows the package bump view. Table 5. Legend/abbreviations used in the pinout table Name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after ...
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Pinouts and pin description Table 5. Legend/abbreviations used in the pinout table (continued) Name Abbreviation Alternate Functions selected through GPIOx_AFR registers functions Additional Functions directly selected/enabled through peripheral registers functions 44/180 Definition Doc ID 022152 Rev 3 STM32F405xx, STM32F407xx ...
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STM32F405xx, STM32F407xx Table 6. STM32F40x pin and ball definitions Pin number (function after - - ...
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Pinouts and pin description Table 6. STM32F40x pin and ball definitions (continued) Pin number (function after - ...
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STM32F405xx, STM32F407xx Table 6. STM32F40x pin and ball definitions (continued) Pin number (function after PA0-WKUP 14 C10 J10 ...
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Pinouts and pin description Table 6. STM32F40x pin and ball definitions (continued) Pin number (function after ...
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STM32F405xx, STM32F407xx Table 6. STM32F40x pin and ball definitions (continued) Pin number (function after - P10 R10 N11 ...
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Pinouts and pin description Table 6. STM32F40x pin and ball definitions (continued) Pin number (function after - - - - K12 H12 J12 P12 92 ...
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STM32F405xx, STM32F407xx Table 6. STM32F40x pin and ball definitions (continued) Pin number (function after - - 60 82 M15 101 - - - 83 - 102 - - - 84 J13 103 - M14 104 - F1 ...
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Pinouts and pin description Table 6. STM32F40x pin and ball definitions (continued) Pin number (function after 100 F15 119 101 E15 120 102 D15 121 103 C15 122 ...
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STM32F405xx, STM32F407xx Table 6. STM32F40x pin and ball definitions (continued) Pin number (function after 109 A14 137 (JTCK-SWCLK 110 A13 138 111 B14 139 112 B13 140 53 ...
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Pinouts and pin description Table 6. STM32F40x pin and ball definitions (continued) Pin number (function after - - - 125 B10 153 - - - 126 B9 154 - - - 127 B8 155 - - - 128 A8 156 ...
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STM32F405xx, STM32F407xx Table 6. STM32F40x pin and ball definitions (continued) Pin number (function after 137 B5 165 138 D6 166 139 A5 167 140 B4 168 - - ...
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Pinouts and pin description 5. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low). Table 7. ...
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STM32F405xx, STM32F407xx Table 7. FSMC pin definition (continued) (1) Pins CF PD8 D13 PD9 D14 PD10 D15 PD11 PD12 PD13 PD14 D0 PD15 D1 PG2 PG3 PG4 PG5 PG6 PG7 PD0 D2 PD1 D3 PD3 PD4 NOE PD5 NWE PD6 ...
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Table 8. Alternate function mapping AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 TIM2_CH1 PA0 TIM 5_CH1 TIM8_ETR TIM2_ETR PA1 TIM2_CH2 TIM5_CH2 PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 PA4 TIM2_CH1 PA5 TIM8_CH1N TIM2_ETR PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN ...
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Table 8. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N PB2 JTDO/ PB3 TIM2_CH2 TRACESWO PB4 NJTRST TIM3_CH1 PB5 TIM3_CH2 PB6 TIM4_CH1 PB7 TIM4_CH2 Port B PB8 ...
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Table 8. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PD0 PD1 PD2 TIM3_ETR PD3 PD4 PD5 PD6 PD7 Port D PD8 PD9 PD10 PD11 PD12 TIM4_CH1 PD13 TIM4_CH2 PD14 TIM4_CH3 PD15 TIM4_CH4 PE0 TIM4_ETR ...
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Table 8. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PF0 PF1 PF2 PF3 PF4 PF5 PF6 TIM10_CH1 PF7 TIM11_CH1 Port F PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PG0 PG1 PG2 PG3 PG4 ...
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Table 8. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 Port H PH8 PH9 PH10 TIM5_CH1 PH11 TIM5_CH2 PH12 TIM5_CH3 PH13 TIM8_CH1N PH14 TIM8_CH2N PH15 TIM8_CH3N PI0 ...
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STM32F405xx, STM32F407xx 4 Memory mapping The memory map is shown in Figure 16. STM32F40x memory map Figure 16. Doc ID 022152 Rev 3 Memory mapping 63/180 ...
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Memory mapping Table 9. STM32F40x register boundary addresses Bus Cortex-M4 AHB3 AHB2 64/180 Boundary address 0xE00F FFFF - 0xFFFF FFFF 0xE000 0000 - 0xE00F FFFF 0xA000 1000 - 0xDFFF FFFF 0xA000 0000 - 0xA000 0FFF 0x9000 0000 - 0x9FFF FFFF ...
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STM32F405xx, STM32F407xx Table 9. STM32F40x register boundary addresses (continued) Bus AHB1 Boundary address 0x4004 0000 - 0x4007 FFFF 0x4002 9400 - 0x4003 FFFF 0x4002 9000 - 0x4002 93FF 0x4002 8C00 - 0x4002 8FFF 0x4002 8800 - 0x4002 8BFF 0x4002 8400 ...
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Memory mapping Table 9. STM32F40x register boundary addresses (continued) Bus APB2 66/180 Boundary address 0x4001 4C00 - 0x4001 57FF 0x4001 4800 - 0x4001 4BFF 0x4001 4400 - 0x4001 47FF 0x4001 4000 - 0x4001 43FF 0x4001 3C00 - 0x4001 3FFF 0x4001 ...
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STM32F405xx, STM32F407xx Table 9. STM32F40x register boundary addresses (continued) Bus APB1 Boundary address 0x4000 7800 - 0x4000 7FFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF 0x4000 6400 ...
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Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
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STM32F405xx, STM32F407xx 5.1.6 Power supply scheme Figure 19. Power supply scheme 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate ...
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Electrical characteristics 5.1.7 Current consumption measurement Figure 20. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Current permanent damage to the device. These are stress ratings only and functional operation ...
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STM32F405xx, STM32F407xx Table 11. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...
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Electrical characteristics Table 13. General operating conditions (continued) Symbol Parameter V When the internal regulator is ON, CAP1 V and V CAP_1 CAP_2 connect a stabilization capacitor. When the internal regulator is OFF V CAP2 (BYPASS_REG connected ...
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STM32F405xx, STM32F407xx Table 14. Limitations depending on the operating power supply range Maximum Operating power ADC supply operation range frequency (f 16 MHz with Conversion V =1 time up to (2) 2.1 V memory wait 1.2 Msps 18 ...
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Electrical characteristics 5.3.2 VCAP1/VCAP2 external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor C the VCAP1/VCAP2 pins. C Figure 21. External capacitor C 1. Legend: ESR is the equivalent series resistance. Table 15. VCAP1/VCAP2 operating ...
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STM32F405xx, STM32F407xx 5.3.5 Embedded reset and power control block characteristics The parameters given in temperature and V Table 18. Embedded reset and power control block characteristics Symbol Programmable voltage V PVD detector level selection (3) V PVD hysteresis PVDhyst Power-on/power-down ...
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Electrical characteristics Table 18. Embedded reset and power control block characteristics (continued) Symbol Brownout level 1 V BOR1 threshold Brownout level 2 V BOR2 threshold Brownout level 3 V BOR3 threshold 1.2 V domain V 12 voltage (3) V BOR ...
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STM32F405xx, STM32F407xx Typical and maximum current consumption The MCU is placed under the following conditions: ● At startup, all I/O pins are configured as analog inputs by firmware. ● All peripherals are disabled except explicitly mentioned. ● ...
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Electrical characteristics 3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption should be considered. 4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power ...
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STM32F405xx, STM32F407xx Figure 22. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running ...
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Electrical characteristics Figure 24. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF Figure 25. Typical current consumption vs temperature, Run mode, code with data processing running ...
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STM32F405xx, STM32F407xx Table 21. Typical and maximum current consumption in Sleep mode Symbol Parameter External clock all peripherals enabled Supply current Sleep mode External clock peripherals disabled 1. Based on characterization, tested in production ...
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Electrical characteristics Table 22. Typical and maximum current consumptions in Stop mode Symbol Parameter Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed Supply current oscillator OFF (no independent watchdog) in Stop mode with main Flash in ...
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STM32F405xx, STM32F407xx Table 24. Typical and maximum current consumptions in V Symbol Parameter Backup SRAM ON, low-speed oscillator and RTC ON Backup Backup SRAM OFF, low-speed I domain supply oscillator and RTC ON DD_VBAT current Backup SRAM ON, RTC OFF ...
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Electrical characteristics Figure 27. Typical V current consumption (LSE and RTC ON/backup RAM ON) BAT I/O system current consumption The current consumption of the I/O system has two components: static ...
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STM32F405xx, STM32F407xx voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where I is the current sunk by a switching I/O to charge/discharge the capacitive load ...
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Electrical characteristics Table 25. Switching output I/O current consumption Symbol Parameter I/O switching I DDIO current the PCB board capacitance including the pad pin This test is performed by cutting the LQFP package pin ...
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STM32F405xx, STM32F407xx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in under the following conditions: ● At startup, all I/O pins are configured as analog pins by firmware. ● All peripherals are disabled unless otherwise ...
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Electrical characteristics Table 26. Peripheral current consumption (continued) Peripheral AHB3 APB1 88/180 (1) 168 MHz FSMC TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM12 TIM13 TIM14 PWR USART2 USART3 UART4 UART5 I2C1 I2C2 I2C3 (2) SPI2/I2S2 0.17/0.16 (2) SPI3/I2S3 0.16/0.14 CAN1 ...
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STM32F405xx, STM32F407xx Table 26. Peripheral current consumption (continued) Peripheral APB2 1. HSE oscillator with 4 MHz crystal and PLL are ON. 2. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral. 3. EN1 ...
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Electrical characteristics 5.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 28. High-speed external user clock ...
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STM32F405xx, STM32F407xx Figure 28. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) External clock source Figure 29. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) External ...
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Electrical characteristics Table 30. HSE 4-26 MHz oscillator characteristics Symbol f Oscillator frequency OSC_IN R Feedback resistor F I HSE current consumption DD g Oscillator transconductance m (3) t Startup time SU(HSE 1. Resonator characteristics given by the crystal/ceramic resonator ...
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STM32F405xx, STM32F407xx Table 31. LSE oscillator characteristics (f Symbol R Feedback resistor F I LSE current consumption DD g Oscillator Transconductance m (2) t startup time SU(LSE) 1. Guaranteed by design, not tested in production the startup ...
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Electrical characteristics 5.3.9 Internal clock source characteristics The parameters given in ambient temperature and V High-speed internal (HSI) RC oscillator Low-speed internal (LSI) RC oscillator Table 32. HSI oscillator characteristics Symbol Parameter f Frequency HSI Accuracy of the HSI ACC ...
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STM32F405xx, STM32F407xx Figure 32. ACC 5.3.10 PLL characteristics The parameters given in temperature and V Table 34. Main PLL characteristics Symbol Parameter (1) f PLL input clock PLL_IN f PLL multiplier output clock PLL_OUT 48 MHz PLL multiplier output f ...
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Electrical characteristics Table 34. Main PLL characteristics (continued) Symbol Parameter Cycle-to-cycle jitter Period Jitter (3) Jitter Main clock output (MCO) for RMII Ethernet Main clock output (MCO) for MII Ethernet Bit Time CAN jitter (4) I PLL power consumption on ...
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STM32F405xx, STM32F407xx Table 35. PLLI2S (audio PLL) characteristics Symbol Parameter PLLI2S power consumption on (5) I DD(PLLI2S PLLI2S power consumption on (5) I DDA(PLLI2S) V DDA 1. TBD stands for “to be defined”. 2. Take care of using ...
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Electrical characteristics 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 36. SSCG parameters constraint Symbol f Mod md MODEPER * INCSTEP 1. Guaranteed by design, not ...
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STM32F405xx, STM32F407xx Figure 33 and Figure 34 down spread modes, where PLL_OUT T is the modulation period. mode md is the modulation depth. Figure 33. PLL output clock waveforms in center spread mode Figure 34. PLL output ...
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Electrical characteristics Table 38. Flash memory programming Symbol t Word programming time prog t Sector (16 KB) erase time ERASE16KB t Sector (64 KB) erase time ERASE64KB t Sector (128 KB) erase time ERASE128KB t Mass erase time ME V ...
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STM32F405xx, STM32F407xx Table 39. Flash memory programming with V Symbol Minimum current sunk the V Cumulative time during (3) t VPP which V 1. Guaranteed by design, not tested in production. 2. The ...
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Electrical characteristics Table 41. EMS characteristics Symbol Voltage limits to be applied on any I/O pin to V FESD induce a functional disturbance Fast transient voltage burst limits applied through 100 EFTB pins to ...
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STM32F405xx, STM32F407xx Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC standard which specifies the test board and the pin loading. Table 42. EMI characteristics Symbol Parameter V = 3.3 V, ...
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Electrical characteristics Static latchup Two complementary static tests are required on six parts to assess the latchup performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and ...
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STM32F405xx, STM32F407xx 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 46. I/O static characteristics Symbol Parameter V Input low level voltage IL (2) TTa/TC I/O input ...
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Electrical characteristics All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, ...
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STM32F405xx, STM32F407xx 4. Based on characterization data, not tested in production. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 48, respectively. Unless otherwise specified, the parameters given in performed under the ambient temperature ...
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Electrical characteristics Table 48. I/O AC characteristics OSPEEDRy [1:0] bit Symbol (1) value F Maximum frequency max(IO)out 11 Output high to low level fall t f(IO)out time Output low to high level rise t r(IO)out time Pulse width of external ...
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STM32F405xx, STM32F407xx 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology connected to a permanent pull-up resistor, R (see PU Unless otherwise specified, the parameters given in performed under the ambient temperature and V in ...
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Electrical characteristics 5.3.18 TIM timer characteristics The parameters given in Refer to Section 5.3.16: I/O port characteristics function characteristics (output compare, input capture, external clock, PWM output). Table 50. Characteristics of TIMx connected to the APB1 domain Symbol t Timer ...
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STM32F405xx, STM32F407xx Table 51. Characteristics of TIMx connected to the APB2 domain Symbol t Timer resolution time res(TIM) Timer external clock f EXT frequency on CH1 to CH4 Res Timer resolution TIM 16-bit counter clock t period when internal clock ...
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Electrical characteristics 2 Table 52 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t ...
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STM32F405xx, STM32F407xx 2 Figure 37 bus AC waveforms and measurement circuit 1. Measurement points are done at CMOS levels: 0.3V Table 53. SCL frequency ( External pull-up resistance For speeds around 200 ...
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Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in are derived from tests performed under the ambient temperature, f supply voltage conditions summarized in Refer to Section 5.3.16: I/O port characteristics function characteristics ...
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STM32F405xx, STM32F407xx Figure 38. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...
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Electrical characteristics Figure 40. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V 116/180 ...
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STM32F405xx, STM32F407xx 2 Table 55 characteristics Symbol clock frequency 1/t c(CK r(CK clock rise and fall time t f(CK) ( valid time v(WS) ( hold ...
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Electrical characteristics 2 Figure 41 slave timing diagram (Philips protocol) CPOL = 0 CPOL = 1 WS input SD transmit SD receive 1. Measurement points are done at CMOS levels: 0.3 × LSB transmit/receive of the ...
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STM32F405xx, STM32F407xx USB OTG FS characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 56. USB OTG FS startup time Symbol (1) t STARTUP 1. Guaranteed by design, not tested in production. ...
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Electrical characteristics Figure 43. USB OTG FS timings: definition of data signal rise and fall time Differen tial data lines V CRS Table 58. USB OTG FS electrical characteristics Symbol t Rise time r t Fall time ...
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STM32F405xx, STM32F407xx USB HS characteristics Table 60 shows the USB HS operating voltage. Table 60. USB HS DC electrical characteristics Symbol Input level V 1. All the voltages are measured from the local ground potential. Table 61. USB HS clock ...
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Electrical characteristics Table 62. ULPI timing Control in (ULPI_DIR) setup time Control in (ULPI_NXT) setup time Control in (ULPI_DIR, ULPI_NXT) hold time Data in setup time Data in hold time Control out (ULPI_STP) setup time and hold time Data out ...
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STM32F405xx, STM32F407xx Table 65 gives the list of Ethernet MAC signals for the RMII and corresponding timing diagram. Figure 46. Ethernet RMII timing diagram RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV Table 65. Dynamics characteristics: Ethernet MAC signals for RMII Symbol t ...
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Electrical characteristics Table 66. Dynamics characteristics: Ethernet MAC signals for MII Symbol t Receive data setup time su(RXD) t Receive data hold time ih(RXD) t Data valid setup time su(DV) t Data valid hold time ih(DV) t Error setup time ...
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STM32F405xx, STM32F407xx Table 67. ADC characteristics (continued) Symbol Parameter Regular trigger conversion (4) t latr latency (4) t Sampling time S (4) t Power-up time STAB Total conversion time (including (4) t CONV sampling time) Sampling rate ( ...
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Electrical characteristics 7. For external triggers, a delay of 1/f Equation 1: R AIN The formula above allowed for an error below 1/4 of LSB (from 12-bit resolution) and k is the number of sampling periods defined ...
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STM32F405xx, STM32F407xx Figure 48. ADC accuracy characteristics 1. See also Table 68. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line Total Unadjusted Error: maximum deviation between the actual and ...
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Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in depending on whether V ceramic (good quality). They should be placed them as close as possible to the chip. Figure 50. Power supply and reference ...
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STM32F405xx, STM32F407xx 5.3.21 Temperature sensor characteristics Table 69. TS characteristics Symbol ( linearity with temperature L SENSE (1) Avg_Slope Average slope (1) V Voltage at 25 °C 25 (2) t Startup time START (3)(2) T ADC sampling time ...
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Electrical characteristics 5.3.24 DAC electrical characteristics Table 72. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (2) R Resistive load with buffer ON LOAD Impedance output with buffer ( ...
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STM32F405xx, STM32F407xx Table 72. DAC characteristics (continued) Symbol Parameter Integral non linearity (difference between measured value at Code i (3) INL and the value at Code line drawn between Code 0 and last Code 1023) Offset error ...
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Electrical characteristics Figure 52. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. ...
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STM32F405xx, STM32F407xx Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 73. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t ...
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Electrical characteristics Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 74. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t FSMC_NE ...
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STM32F405xx, STM32F407xx Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 75. Asynchronous multiplexed PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low ...
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Electrical characteristics Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 76. Asynchronous multiplexed PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low ...
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STM32F405xx, STM32F407xx Synchronous waveforms and timings Figure 57 through Table 80 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ...
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Electrical characteristics Table 77. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x=0..2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x= 0…2) d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low d(CLKL-NADVL) t FSMC_CLK ...
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STM32F405xx, STM32F407xx Figure 58. Synchronous multiplexed PSRAM write timings Table 78. Synchronous multiplexed PSRAM write timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x=0..2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x= 0…2) d(CLKL-NExH) t FSMC_CLK ...
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Electrical characteristics Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings Table 79. Synchronous non-multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x=0..2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x= 0…2) d(CLKL-NExH) t FSMC_CLK ...
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STM32F405xx, STM32F407xx Figure 60. Synchronous non-multiplexed PSRAM write timings Table 80. Synchronous non-multiplexed PSRAM write timings Symbol t w(CLK) d(CLKL-NExL d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t d(CLKL-NBLH) 1. ...
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Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 61 through provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ...
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STM32F405xx, STM32F407xx Figure 62. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t v(NWE-D) Doc ID 022152 ...
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Electrical characteristics Figure 63. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 144/180 t v(NCE4_1-A) High ...
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STM32F405xx, STM32F407xx Figure 64. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 65. PC Card/CompactFlash controller ...
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Electrical characteristics Figure 66. PC Card/CompactFlash controller waveforms for I/O space write access Table 81. Switching characteristics for PC Card/CF read and write cycles in attribute/common space Symbol t FSMC_Ncex low to FSMC_Ay valid v(NCEx-A) t FSMC_NCEx high to FSMC_Ax ...
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STM32F405xx, STM32F407xx Table 82. Switching characteristics for PC Card/CF read and write cycles (1)(2) in I/O space Symbol t FSMC_NIOWR low width w(NIOWR) t FSMC_NIOWR low to FSMC_D[15:0] valid v(NIOWR-D) t FSMC_NIOWR high to FSMC_D[15:0] invalid h(NIOWR-D) t FSMC_NCE4_1 low ...
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Electrical characteristics Figure 67. NAND controller waveforms for read access Figure 68. NAND controller waveforms for write access 148/180 Doc ID 022152 Rev 3 STM32F405xx, STM32F407xx ...
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STM32F405xx, STM32F407xx Figure 69. NAND controller waveforms for common memory read access Figure 70. NAND controller waveforms for common memory write access Table 83. Switching characteristics for NAND Flash read cycles Symbol t FSMC_NOE low width w(N0E) t FSMC_D[15-0] valid ...
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Electrical characteristics Table 84. Switching characteristics for NAND Flash write cycles Symbol t w(NWE) t v(NWE-D) t h(NWE-D) t d(D-NWE) t d(ALE-NWE) t h(NWE-ALE pF. L 5.3.26 Camera interface (DCMI) timing specifications Table 85. DCMI characteristics ...
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STM32F405xx, STM32F407xx Figure 72. SD default mode Table 86 MMC characteristics Symbol Clock frequency in data transfer f PP mode - SDIO_CK/f t Clock low time, f W(CKL) t Clock high time, f W(CKH) t Clock rise time ...
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Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...
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STM32F405xx, STM32F407xx Figure 73. WLCSP90 - 0.400 mm pitch wafer level chip size package outline Table 88. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data Symbol Min A 0.520 A1 0.165 A2 0.350 b 0.240 D ...
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Package characteristics Figure 74. LQFP64 – pin low-profile quad flat package outline Drawing is not to scale. Table 89. LQFP64 – pin low-profile quad flat package mechanical ...
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STM32F405xx, STM32F407xx Figure 75. LQFP64 recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters 0.5 12.7 10.3 10 7.8 12.7 Doc ID 022152 Rev 3 Package characteristics 33 0 1.2 ...
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Package characteristics Figure 76. LQFP100 100-pin low-profile quad flat package outline 1. Drawing is not to scale. Table 90. LQPF100 – 100-pin low-profile quad flat package mechanical data Symbol Min A A1 ...
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STM32F405xx, STM32F407xx Figure 77. LQFP100 recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. Doc ID 022152 Rev 3 Package characteristics 157/180 ...
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Package characteristics Figure 78. LQFP144 mm, 144-pin low-profile quad flat package outline 1. Drawing is not to scale. Table 91. LQFP144 mm, 144-pin low-profile quad flat package mechanical data Symbol Min A A1 0.050 ...
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STM32F405xx, STM32F407xx Figure 79. LQFP144 recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. Doc ID 022152 Rev 3 Package characteristics 159/180 ...
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Package characteristics Figure 80. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline 1. Drawing is not to scale. Table 92. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × ...
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STM32F405xx, STM32F407xx Figure 81. LQFP176 mm, 176-pin low-profile quad flat package outline 1. Drawing is not to scale. Table 93. LQFP176 mm, 176-pin low-profile quad flat package mechanical data Symbol Min A A1 0.050 ...
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Package characteristics Figure 82. LQFP176 recommended footprint 1. Dimensions are expressed in millimeters. 162/180 Doc ID 022152 Rev 3 STM32F405xx, STM32F407xx ...
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STM32F405xx, STM32F407xx 6.2 Thermal characteristics The maximum chip-junction temperature, T using the following equation: Where: max is the maximum ambient temperature in °C, ● Θ is the package junction-to-ambient thermal resistance, in °C/W, ● JA ● P max ...
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Part numbering 7 Part numbering Table 95. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 405 = STM32F40x, connectivity 407= STM32F40x, connectivity, camera interface, Ethernet Pin count ...
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STM32F405xx, STM32F407xx Appendix A Application block diagrams A.1 Main applications versus package Table 96 gives examples of configurations for each package. Table 96. Main applications versus package for STM32F407xx microcontrollers 64 pins Config Config 1 2 OTG ...
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Application block diagrams A.2 Application example with regulator OFF Figure 83. Regulator OFF/internal reset ON 1. This mode is available only on UFBGA176 and WLCSP90 packages. Figure 84. Regulator OFF/internal reset OFF 1. This mode is available only on UFBGA176 ...
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STM32F405xx, STM32F407xx A.3 USB OTG full speed (FS) interface solutions Figure 85. USB controller configured as peripheral-only and used in Full speed mode 1. External voltage regulator only needed when building The same application can be developed ...
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Application block diagrams Figure 87. USB controller configured in dual mode and used in full speed mode 1. External voltage regulator only needed when building The current limiter is required only if the application has to support ...
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STM32F405xx, STM32F407xx A.4 USB OTG high speed (HS) interface solutions Figure 88. USB controller configured as peripheral, host, or dual-mode and used in high speed mode possible to use MCO1 or MCO2 to save a crystal. It ...
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Application block diagrams A.5 Complete audio player solutions Two solutions are offered, illustrated in Figure 89 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I clock (0.5% ...
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STM32F405xx, STM32F407xx Figure 91. Audio player solution using PLL, PLLI2S, USB and 1 crystal Figure 92. Audio PLL (PLLI2S) providing accurate I2S clock Doc ID 022152 Rev 3 Application block diagrams 171/180 ...
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Application block diagrams Figure 93. Master clock (MCK) used to drive the external audio DAC 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Figure 94. Master clock (MCK) not used ...
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STM32F405xx, STM32F407xx A.6 Ethernet interface solutions Figure 95. MII mode using a 25 MHz crystal 1. f must be greater than 25 MHz. HCLK 2. Pulse per second when using IEEE1588 PTP optional signal. Figure 96. RMII with a 50 ...
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Application block diagrams Figure 97. RMII with a 25 MHz crystal and PHY with PLL 1. f must be greater than 25 MHz. HCLK 2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL ...
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STM32F405xx, STM32F407xx 8 Revision history Table 97. Document revision history Date Revision 15-Sep-2011 24-Jan-2012 1 Initial release. Added WLCSP90 package on cover page. Renamed USART4 and USART5 into UART4 and UART5, respectively. Updated number of USB OTG HS and FS ...
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Revision history Table 97. Document revision history (continued) Date Revision 24-Jan-2012 (continued) 176/180 Added V12 in Table 18: Embedded reset and power control block characteristics. Updated Table 19: Typical and maximum current consumption in Run mode, code with data processing ...
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STM32F405xx, STM32F407xx Table 97. Document revision history (continued) Date Revision 24-Jan-2012 (continued) Updated Table 59: USB FS clock timing parameters HS clock timing parameters Updated Table 67: ADC characteristics. Updated Table 68: ADC accuracy at f Updated Note 1 in ...
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Revision history Table 97. Document revision history (continued) Date Revision 31-May-2012 178/180 Updated Figure 5: STM32F40x block diagram ON/internal reset OFF Added SDIO, added notes related to FSMC and SPI/I2S in STM32F405xx and STM32F407xx: features and peripheral Starting from Silicon ...
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STM32F405xx, STM32F407xx Table 97. Document revision history (continued) Date Revision 31-May-2012 (continued) Removed f typical value in HSE_ext clock characteristics. Updated characteristics and Table 31: LSE oscillator characteristics (f 32.768 kHz). Added f maximum value in PLL48_OUT characteristics. Modified equation ...
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