MT46H16M16LFBF-6 IT:A Micron Technology Inc, MT46H16M16LFBF-6 IT:A Datasheet - Page 55

• Manufacturer Part Number: MT46H16M16LFBF-6 IT:A
• Description: IC DDR SDRAM 256MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H16M16LFBF-6 IT:A

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant
• Other names: Q3368612

PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
10. A READ command may be applied after the completion of the WRITE burst; otherwise, a
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a
From Command
WRITE
(with auto precharge)
READ
(with auto precharge)
This device supports concurrent auto precharge such that when a read with auto precharge
is enabled or a write with auto precharge is enabled, any command to other banks is sup-
ported, as long as that command does not interrupt the read or write data transfer already
in process. In either case, all other related limitations apply (that is, contention between
read data and write data must be avoided).
3b. The minimum delay from a READ or WRITE command with auto precharge enabled to a
command to a different bank is summarized below.
CL
are idle.
represented by the current state only.
auto precharge enabled and READs or WRITEs with auto precharge disabled.
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
BURST TERMINATE must be used to end the WRITE burst prior to asserting a READ
command.
RU
= CAS latency (CL) rounded up to the next integer; BL = burst length
To Command
READ or
READ (with auto precharge)
WRITE or
WRITE (with auto precharge)
PRECHARGE
ACTIVE
READ or
READ (with auto precharge)
WRITE or
WRITE (with auto precharge)
PRECHARGE
ACTIVE
55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
(with Concurrent Auto Precharge)
[1 + (BL/2)]
[CL
Minimum Delay
©2005 Micron Technology, Inc. All rights reserved.
RU
(BL/2) ×
(BL/2)
+ (BL/2)]
1
1
1
1
t
t
t
t
CK
CK
CK
CK
t
CK +
t
CK
t
CK
Operations
t
t
CK
WTR