IS43R32800B-5BL-TR ISSI, Integrated Silicon Solution Inc, IS43R32800B-5BL-TR Datasheet - Page 15

• Manufacturer Part Number: IS43R32800B-5BL-TR
• Description: IC DDR SDRAM 256MBIT 144BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32800B-5BL-TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: Mini BGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 400mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43R32800B
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
03/19/08
tDQS CK DQS O utput access time from CLK //CL K
tWPR ES Write preamble setup time
AC TIMING REQUIREMENTS
tDQS Q DQ V alid data delay time from DQS
tDQS H DQS input High level width
tWPR E W rite preamble
Sy mbol
tDQS S W rite command to first DQS latchingtransition
tDQS L D QS input Low level width
tWPST
tDIP W D Q and DM input pulse width (for each input)
tMRD
tRPST
tRPR E R ead preamble
tIPW
tQHS
tDSH
tDSS
tAC
tCK
tDH
tQH
tCH
tCL
tDS
tHZ
tHP
tLZ
tIH
tIS
D Q Output access time from CLK //CL K
C LK Low level width
I nput Setup time (DQ ,DM)
I nput Hold time(DQ,DM )
DQ output hold time from DQS (per access)
C LK Highlevel width
CL K c ycle time
Control & address input pulse width(for eachinput)
Data-out-highimpeda nce time from CLK //CL K
Data-out-low impedan ce time fromCL K//CLK
C lock half period
Data hold skew factor (for DQ S & a ssociated DQ signals)
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
Mode Register Set command cycle time
Write postamble
I nput Setup time (address and control)
I nput Hold time (address and control)
Read postamble
AC Ch arac terist i cs P aram eter
CL =3.0
CL =2.5
CL =2.0
tCHmin
tHP-tQHS
tCLmin or
-0.70
Min.
0.45
0.72
0.35
0.25
0.45
1.75
0.35
-0.70
-0.6
7.5
0.4
2.2
0.2
0.4
0.6
0.6
0.4
5
5
2
0
0.4
0.2
0.9
-5
+0.70
+0.70
+0.70
+0.6
Max
0.55
0.55
0.40
0.50
1.25
7.5
0.6
0.6
1.1
12
12
tCHmin
tHP-tQHS
tCLmin or
-0.70
-0.60
-0.70
0.45
0.45
0.45
0.45
1.75
0.75
0.35
0.35
0.25
0.75
0.75
Min.
7.5
2.2
0.2
0.2
0.4
0.4
0.9
6
6
2
0
-6
+0.70
+0.60
+0.70
+0.70
Max
0.55
0.55
0.45
0.55
1.25
0.6
0.6
1.1
12
12
12
tCHmin
tHP-tQHS
tCLmin or
-0.75
-0.75
-0.75
Min.
0.45
0.45
1.75
0.75
0.35
0.35
0.25
7.5
7.5
7.5
0.5
0.5
2.2
0.2
0.4
0.4
0.2
0.9
0.9
0.9
2
0
-75
+0.75
+0.75
+0.75
+0.75
Max
0.55
0.55
0.75
1.25
0.5
0.6
0.6
1.1
12
12
12
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Un it
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1 5
14
14
20
16
19
19
15