IS43R32800B-5BL-TR ISSI, Integrated Silicon Solution Inc, IS43R32800B-5BL-TR Datasheet - Page 17

• Manufacturer Part Number: IS43R32800B-5BL-TR
• Description: IC DDR SDRAM 256MBIT 144BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32800B-5BL-TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: Mini BGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 400mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not
ring back above (below) the DC i nput LO W ( HI GH ) l evel.
5. VR EF is expect ed to be equa l to 0.5*V
same. Peak-to-peak noise on VR EF may not exceed +2% of the DC value.
this CL K e dge. A vali d transition is defined as monotonic, and meeting the inputslew rate specifications of the device.
When no writes were previously in progress on the bus, DQS wil l be transitioning from Hi gh-Z to logic L OW . I f a
17. A maximum of eight AUT O R EF RE SH commands can be posted to any given DDR SD RA M device.
18. tX PR D should be 200 tCLK in the condition of the unstable CL K o peration during the power down mode.
19. For command/address and CK & / CK slew rate > 1.0V/ns.
20. Mi n (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the
devi ce.
Notes
1. Al l voltages referenced to Vss.
2. Tests for AC timing, I DD, and electrical, AC and DC characteristics, may be conducted at nominal reference/suppl y
voltagelevels, but the related specifications and device operation are guaranteed for the full voltagerange specified.
3. AC timing and IDD tests may use a VI L to V IH swing of up to 1.5V i n the test environment, but inputtiming is still
referenced to VR EF (or to the crossing point for CK //CK), and parameter specifications are guaranteedfor the
specified AC input levels under normal use conditions. The minimum slew rate for the inputsignals is 1V/ns in the
rangebetween V IL (AC) and V IH (AC) .
4. The AC and DC input level specifications are as defined in the SST L_ 2 Standard (i.e. the receiver will effectively
6. VT T i s not appl i ed directly to the device. VT T i s a system supply for signal termination resistors, is expected to be
set equal to V RE F, and must track variations in the DC l evel of VR EF .
7. VI D i s the magnitude of the difference between the input level on CLK and the inputlevel on /CL K.
8. The value of VI X i s expected to equa l 0.5*V
of the same.
9. Enables on-chip refresh and address counters.
10. ID D specifi cations are tested after the device is properly initialized.
11. This parameter is sampled. V
V
matched in loading (to facili tatetrace matching at the board level).
12. The CLK// CL K i nput reference level (for timing referenced to CL K //CLK ) i s the point at which CL K a nd /CLK
cross; the inputreference level for signals other than CLK// CL K, is VR EF .
13. Input s are not recognized as valid until V RE F stabili zes. Ex ception: during the period before V RE F stabili zes,
CKE< 0.3V
14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. T hese parameters are not
referenced to a specific voltagelevel, but specify when the device outputis no longer driving (HZ ), or begins driving
(LZ) .
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be vali d (HI GH , L OW , or at some point on a valid transition) on or before
previous write was in progress, DQS could be HIG H, LOW, or transitioning from HI GH to LO W at this time,
depending on tDQSS.
IS43R32800B
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
03/19/08
DDQ
Ti ming patterns:
*100% of datachangi n g at every burst
tCK= min,tRRD =2*tCK,B L= 4,tRCD=3*tCK ,R ead with Autoprecharge
Read:A0 N A1 R0 A2 R1 N R 3 A 0 N A1 R 0 – repeat the same timing with random address changing
Legend: A =Activate,R= Read,P=Precharge,N =NOP
/2, V OUT( PE AK TO PE AK ) = 25mV . D M i nputs are grouped with I/O pins - reflecting the fact that they are
DDQ
is recognized as LOW.
DDQ
= 2.5V+ 0.2V , V
DDQ
of the transmitting device, and to track variations in the DC l evel of the
DDQ
of the transmitting device and must track variations in the DC l evel
DD
= 2.5V + 0.2V , f = 100 MH z, Ta = 25
o
C, VO UT (DC) =
17