IS43R32800B-5BL-TR ISSI, Integrated Silicon Solution Inc, IS43R32800B-5BL-TR Datasheet - Page 25

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IS43R32800B-5BL-TR

Manufacturer Part Number
IS43R32800B-5BL-TR
Description
IC DDR SDRAM 256MBIT 144BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
DDR SDRAMr
Datasheet

Specifications of IS43R32800B-5BL-TR

Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
256M (8Mx32)
Speed
200MHz
Interface
Parallel
Voltage - Supply
2.4 V ~ 2.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
144-BGA
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
700ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.5V
Package Type
Mini BGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
400mA
Pin Count
144
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS43R32800B-5BL-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS43R32800B
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
03/19/08
READ
after the /CAS La tency from the RE AD , followed by (BL-1 ) consecutive data when the Burst Le ngth
is BL . T he start address is specified by A0 -7,9, and the address seque nce of burst data is defined by
the Burst Ty pe. A RE AD command may be applied to any active bank, so the row precharge time
(tRP ) can be hidden behind continuous output data by interleaving the multiple banks. When A8 is
high at a REA D command, the auto-precharge (READA ) is performed. A ny
command(RE AD ,W RI TE,P RE ,A CT ) to the same bank is inhibited till the internal precharge is
complete. T he internal precharge starts at BL/2 after RE AD A. The next ACT command can be
issued after (BL/2+t RP ) from the previous RE AD A.
Af ter tRCD from the bank activation, a REA D command can be issued. 1st Output data is available
A0-7 ,9-11
Command
BA 0,1
/CLK
DQS
CL K
A8
DQ
AC T
Xa
Xa
00
tRCD
Mu lti B ank I nterleaving R EA D ( BL =8, C L=2)
RE AD
00
Y
0
/CAS latency
AC T
Xb
Xb
10
Qa0
Qa1
Qa2
Burst Length
RE AD
Qa3
Y
0
10
Qa4
Qa5
PR E
00
0
Qa6
Qa7
Qb0 Qb1
Qb2 Qb3
Qb4 Qb5
Qb7 Qb8
25

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