IS43R32800B-5BL-TR ISSI, Integrated Silicon Solution Inc, IS43R32800B-5BL-TR Datasheet - Page 27

• Manufacturer Part Number: IS43R32800B-5BL-TR
• Description: IC DDR SDRAM 256MBIT 144BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32800B-5BL-TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: Mini BGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 400mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43R32800B
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
03/19/08
WRITE
row precharge time (tRP ) can be hidden behind continuous input data by interleaving the multiple
A8 is high at a WRI TE command, the auto-precharge(WRI TE A) is performed. Any
the WRI TE command with data strobe input, following (B L- 1) data are written into RA M, when
the Burst Length is BL . T he start address is specified by A0 -7,9, and the address seque nce of burst
data is defined by the Burst Type. A W RI TE command may be applied to any active bank, so the
banks. From the last data to the PR E command, the write recovery time (tWR P) is required. W hen
command(RE AD ,W RI TE,P RE ,A CT ) to the same bank is inhibited till the internal precharge is
complete. T he next AC T c ommand can be issued after tDAL from the last input data cycle.
Af ter tRCD from the bank activation, a WRI TE command can be issued. 1st input data is set from
Command
A0-7 ,9-11
BA 0,1
/CLK
DQS
CL K
A8
DQ
AC T
Xa
Xa
Xa
00
D
tRCD
WR IT E
Ya
00
0
Multi B ank I nterleaving WRITE (B L=8)
Da0
AC T
Xb
Xb
10
Da1
Da2
Da3
D
tRCD
Da4
Da5
WR IT E
Da6
10
Yb
0
Da7
Db0
Db1 Db2
PR E
00
0
Db3
Db4
Db5 Db6
Db7
PR E
10
0
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