M29W128GH70N6E NUMONYX, M29W128GH70N6E Datasheet - Page 17

• Manufacturer Part Number: M29W128GH70N6E
• Description: IC FLASH 128MBIT 70NS 56TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W128GH70N6E

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16Mx8, 8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Package: 56TSOP
• Cell Type: NOR
• Density: 128 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 128KByte x 128
• Timing Type: Asynchronous
• Interface Type: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3
3.1
3.2
3.3
3.4
Bus operations
There are five standard bus operations that control the device. These are bus read (random
and page modes), bus write, output disable, standby and automatic standby.
See
summary. Typical glitches of less than 5 ns on chip enable, write enable, and reset pins are
ignored by the memory and do not affect bus operations.
Bus read
Bus read operations read from the memory cells, or specific registers in the command
interface. To speed up the read operation the memory array can be read in page mode
where data is internally read and stored in a page buffer. The page has a size of 8 words (or
16 bytes) and each word in the page is addressed by the address inputs A2-A0 in x 16
mode and A2-A0 plus DQ15A 1 in byte mode.
A valid bus read operation involves setting the desired address on the address inputs,
applying a Low signal, V
V
waveforms (8-bit
Read AC
Bus write
Bus write operations write to the command interface. A valid bus write operation begins by
setting the desired address on the address inputs. The address inputs are latched by the
command interface on the falling edge of chip enable or write enable, whichever occurs last.
The Data inputs/outputs are latched by the command interface on the rising edge of chip
enable or write enable, whichever occurs first. Output enable must remain High, V
the whole bus write operation. See
Table 27
Output disable
The data inputs/outputs are in the high impedance state when output enable is High, V
Standby
Driving chip enable High in read mode, causes the memory to enter standby mode and the
data inputs/outputs pins are placed in the high-impedance state. To reduce the supply
current to the standby supply current, I
For the standby current level see
During program or erase operations the memory will continue to use the program/erase
supply current, I
IH
. The data inputs/outputs will output the value, see
Table 4: Bus operations, 8-bit mode
and
characteristics, for details of when the output becomes valid.
Table
CC3
mode),
28, Write AC characteristics, for details of the timing requirements.
, for program or erase operations until the operation completes.
IL
Figure 16: Page read AC waveforms (16-bit
, to chip enable and output enable and keeping write enable High,
Table 25: DC
Figure
CC2
and
, chip enable should be held within V
17, and
Table 5: Bus operations, 16-bit mode
characteristics.
Figure
Figure 13: Random read AC
18, Write AC waveforms, and
mode), and
CC
Table 26:
IH
± 0.3 V.
for a
, during
IH
17/94
.