NAND08GW3F2AN6E NUMONYX, NAND08GW3F2AN6E Datasheet - Page 23

• Manufacturer Part Number: NAND08GW3F2AN6E
• Description: IC FLASH 8GBIT SLC 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND08GW3F2AN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

NAND08GW3F2A, NAND16GW3F2A
Figure 8.
6.1.4
RB
I/O
Row Add 1,2,3
code
Cmd
80h
Random data input during sequential data input
Block erase
Erase operations are done one block at a time. An erase operation sets all the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to
1.
2.
3.
The erase operation is initiated on the rising edge of Write Enable, W, after the Confirm
command is issued. The P/E/R controller handles block erase and implements the verify
process.
During the block erase operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completes successfully, the write status bit
SR0 is ‘0’, otherwise it is set to ‘1’ (refer to
5 Add cycles
Address
One bus cycle is required to setup the Block Erase command. Only addresses A19 to
A30 are valid while the addresses A13 to A18 are ignored
Three bus cycles are then required to load the address of the block to be erased. Refer
to
One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
inputs
Col Add 1,2
Table 6: Address definitions
Main area
Data input
Spare
code
area
Cmd
85h
2 Add cycles
Address
Col Add 1,2
for the block addresses of each device
inputs
Section 6.5: Read status
Data input
Figure 9: Block erase
(Program Busy time)
tBLBH2
Confirm
code
10h
Main area
Busy
register).
Read status register
Device operations
70h
Spare
operation):
area
SR0
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